SLOSE86B july 2022 – july 2023 TAS2781
PRODUCTION DATA
A SAR ADC monitors PVDDH voltage, PVDDL voltage and die temperature. The results of these conversions are available via register readback (PVDDH_CNV[11:0], PVDDL_CNV[11:0] and TMP_CNV[7:0] register bits). PVDDH and PVDDL voltage conversions are also used by the limiter and brown out prevention blocks.
By default, PVDDL conversion is enabled along with PVDDH and temperature in both cases, when BOP source is PVDDL (BOP_SRC = 0) or BOP source is PVDDH (BOP_SRC = 1).
The ADC runs at a fixed 192 kHz sample rate with a conversion time of 5.2 µs.
Temperature is sampled once every 18th SAR conversions. Sampling rate for temperature is approximative 10K samples/sec.
PVDDH and PVDDL voltages and the die temperature can be estimated by user using equations from registers in , and .
The register bits content should always be read from MSB to LSB.
The voltage and temperature readings of SAR ADC are also available to the host through the SDOUT pin. Use bits of register from to enable this feature and configure the slots.