SLOSE86B july 2022 – july 2023 TAS2781
PRODUCTION DATA
The power sequence between the supply rails can be applied in any order as long as SDZ pin is held low. Once all supplies are stable the SDZ pin can be set high to initialize the part. After a hardware or software reset additional commands to the device should be delayed for at least 1 ms to allow the OTP memory to load (see section Section 10).
When PVDDL is internally generated (see Section 11.1) it is recommended that the device enters Software Shutdown mode before entering Hardware Shutdown mode. This ensures that PVDDL pin is discharged using the internal 5 kOhms pull down resistor (not present in Hardware Shutdown mode).