The TAS2781 monitors PVDDH supply voltage and the audio signal to automatically decrease gain when the audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time through end of charge battery conditions. The limiter threshold can be configured to track PVDDH below a programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold reduction from PVDDH tracking.

The limiter is enabled by setting the LIM_EN bit register to high.

Configurable attack rate, hold time and release rate are provided to shape the dynamic response of the limiter (LIM_ATK[3:0], LIM_HLD[2:0] and LIM_RLS[3:0] bits of registers from and .

A maximum level of attenuation applied by the limiter is configurable via the LIM_MAX_AT[3:0] bits of register . If the limiter is attacking and if it reaches the maximum attenuation, gain will not be reduced any further.

The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can be configured to track PVDDH below a programmable inflection point with a minimum threshold value. shows the limiter configured to limit to a constant level regardless of PVDDH level. To achieve this behavior, set the limiter maximum threshold to the desired level via the LIM_MAX_TH[31:0] register bits. Set the limiter inflection point (register bits LIM_INF[31:0]) below the minimum allowable PVDDH setting. The limiter minimum threshold, set by register bits LIM_MIN_TH[31:0], does not impact limiter behavior in this use case.

Figure 8-1 Limiter with Fixed Threshold

Figure 8-3 Limiter with Dynamic Threshold

Figure 8-2 Limiter with Inflection Point

Figure 8-4 Limiter with Inflection Point and Minimum Threshold

shows how to configure the limiter to track PVDDH below a threshold without a minimum threshold. Set the LIM_MAX_TH[31:0] register bits to the desired threshold and LIM_INF[31:0] register bits to the desired inflection point where the limiter will begin reducing the threshold with PVDDH. The LIM_SLP[31:0] register bits can be used to change the slope of the limiter tracking with PVDDH. The default value of 1 V/V will reduce the threshold 1 V for every 1 V of drop in PVDDH supply. More aggressive tracking slopes can be programmed if desired. Program the LIM_MIN_TH[31:0] bits below the minimum PVDDH to prevent the limiter from having a minimum threshold reduction when tracking PVDDH.

The limiter with a supply tracking slope can be configured in an alternate way. By setting LIM_DYHDR register bit to 1'b1 in register in , a headroom can be specified as a percentage of the supply voltage using a 1V/V slope by setting LIM_HDR[4:0] register bits. For example if a headroom of -10% is specified, the peak output voltage will be set to be 10% higher than PVDDH. In this use case presented in the limiting begins for signals above the supply voltage and will result in a fixed clipping. If a positive headroom of +10% is specified the peak output voltage will be dynamically set 10% below the current PVDDH. In this use case the limiting will begin at signal levels lower than the supply voltage and prevent clipping from occurring.

To achieve a limiter that tracks PVDDH only up to a minimum threshold, configure the limiter LIM_MAX_TH[31:0] and LIM_SLP[31:0] register bits as in the previous examples. Then additionally set the LIM_MIN_TH[31:0] register bits to the desired minimum threshold. Supply voltage below this minimum threshold will not continue to decrease the signal output voltage. This is shown in .

By setting register bit LIM_DYHDR to low the limiter mechanism depends on settings for maximum and minimum thresholds, inflection point and slope. By default this bit is high and the limiter dynamic headroom is enabled.