SLASEG6 Data sheet

8.3.3 DAC and DSP Clocking

The TAS3251 front-end (DAC and DSP) has flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio Interface in one form or another. See section Oscillator for Output Power Stagefor setting the output stage oscillator and switching frequency.

Figure 21. Audio Flow with Respective Clocks

Figure 21 shows the basic data flow at basic sample rate (f_S). When the data is brought into the serial audio interface, the data is processed, interpolated and modulated to 128 × f_S before arriving at the current segments for the final digital to analog conversion.

Figure 22 shows the clock tree.

Figure 22. TAS3251 Clock Distribution Tree

The Serial Audio Interface typically has 4 connection pins which are listed as follows:

MCLK (System Master Clock)
SCLK (Serial or Bit Clock)
LRCK/FS (Left-Right Word Clock and Frame Sync)
SDIN (Input Data)
SDOUT can be used to output pre- or post-processed DSP data for use externally (See theSDOUT Port and Hardware Control Pins section)

The device has an internal PLL that is used to take either MCLK or SCLK and create the higher rate clocks required by the DSP and the DAC clock.

In situations where the highest audio performance is required, bringing MCLK to the device along with SCLK and LRCK/FS is recommended. The device should be configured so that the PLL is only providing a clock source to the DSP. All other clocks are then a division of the incoming MCLK. To enable the MCLK as the main source clock, with all others being created as divisions of the incoming MCLK, set the DAC CLK source mux (SDAC in Figure 22) to use MCLK as a source, rather than the output of the MCLK/PLL mux.

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Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8.3.3 DAC and DSP Clocking