SLASEG6B May 2018 – June 2020 TAS3251
PRODUCTION DATA.
The TAS3251 output power stage does not require a specific power-up sequence, but it is recommended to hold RESET low for a minimum of 400 ms after PVDD supply voltage is powered on. The outputs of the half-bridges remain in a high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pull-down of the half-bridge output as well as initiating a controlled ramp up sequence of the output voltage.
When RESET is released to turn on TAS3251, FAULT signal will output low and AVDD voltage regulator will be enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Next a pre-charge time begins to stabilize the DC voltage across the input AC coupling capacitors, followed by the ramp up output power stage sequence .