SLASEG6B May 2018 – June 2020 TAS3251
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | CMDP | ||||||
R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | Reserved | Reserved | ||
2-0 | CMDP | R/W | 0 | Clock Missing Detection Period – These bits set how long both SCLK and LRCLK keep low before the audio clocks deemed missing and the DAC transitions to powerdown mode.
000: about 1 second
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