SLAS624A November   2008  – November 2016 TAS5342LA

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Specifications (BTL)
    7. 6.7 Audio Specifications (Single-Ended Output)
    8. 6.8 Audio Specifications (PBTL)
    9. 6.9 Typical Characteristics
      1. 6.9.1 BTL Configuration
      2. 6.9.2 SE Configuration
      3. 6.9.3 PBTL Configuration
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Mid Z Sequence Compatibility
      2. 7.3.2 Device Protection System
      3. 7.3.3 Use Of TAS5342LA In High-Modulation-Index Capable Systems
      4. 7.3.4 Overcurrent (OC) Protection With Current Limiting and Overload Detection
      5. 7.3.5 Pin-To-Pin Short Circuit Protection System (PPSC)
      6. 7.3.6 Overtemperature Protection
      7. 7.3.7 Undervoltage Protection (UVP) and Power-On Reset (POR)
      8. 7.3.8 Error Reporting
      9. 7.3.9 Device Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Power-Up/Power-Down Sequence
        1. 7.4.1.1 Powering Up
        2. 7.4.1.2 Powering Down
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Differential (2N) BTL Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 PCB Material Recommendation
          2. 8.2.1.2.2 PVDD Capacitor Recommendation
          3. 8.2.1.2.3 Decoupling Capacitor Recommendations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Non-Differential (1N) BTL
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Typical SE Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
      4. 8.2.4 Typical Differential (2N) PBTL Application
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Application Curves
      5. 8.2.5 Typical Non-Differential (1N) PBTL
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Application Curves
    3. 8.3 Systems Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DDV Package
44-Pin HTTSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 11 P Analog ground
BST_A 43 P Bootstrap pin, A-Side
BST_B 34 P Bootstrap pin, B-Side
BST_C 33 P Bootstrap pin, C-Side
BST_D 24 P Bootstrap pin, D-Side
GND 10 P Ground
GND_A 38 P Power ground for half-bridge A
GND_B 37 P Power ground for half-bridge B
GND_C 30 P Power ground for half-bridge C
GND_D 29 P Power ground for half-bridge D
GVDD_A 44 P Gate-drive voltage supply; A-Side
GVDD_B 1 P Gate-drive voltage supply; B-Side
GVDD_C 22 P Gate-drive voltage supply; C-Side
GVDD_D 23 P Gate-drive voltage supply; D-Side
M1 15 I Mode selection pin (LSB)
M2 14 I Mode selection pin
M3 13 I Mode selection pin (MSB)
NC 3, 4, 19, 20, 25, 42 – No connect. Pins may be grounded.
OC_ADJ 9 O Analog overcurrent programming pin
OTW 2 O Overtemperature warning signal, open-drain, active-low
OUT_A 39 O Output, half-bridge A
OUT_B 36 O Output, half-bridge B
OUT_C 31 O Output, half-bridge C
OUT_D 28 O Output, half-bridge D
PVDD_A 40, 41 P Power supply input for half-bridge A
PVDD_B 35 P Power supply input for half-bridge B
PVDD_C 32 P Power supply input for half-bridge C
PVDD_D 26, 27 P Power supply input for half-bridge D
PWM_A 6 I PWM Input signal for half-bridge A
PWM_B 8 I PWM Input signal for half-bridge B
PWM_C 16 I PWM Input signal for half-bridge C
PWM_D 18 I PWM Input signal for half-bridge D
RESET_AB 7 I Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD 17 I Reset signal for half-bridge C and half-bridge D, active-low
SD 5 O Shutdown signal, open-drain, active-low
VDD 21 P Input power supply
VREG 12 P Internal voltage regulator