SLOSE41C April   2020  – September 2023 TAS5441-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for I2C Interface Signals
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Audio Input and Preamplifier
      2. 7.3.2 Pulse-Width Modulator (PWM)
      3. 7.3.3 Gate Drive
      4. 7.3.4 Power FETs
      5. 7.3.5 Load Diagnostics
        1. 7.3.5.1 Load Diagnostics Sequence
        2. 7.3.5.2 Faults During Load Diagnostics
      6. 7.3.6 Protection and Monitoring
      7. 7.3.7 I2C Serial Communication Bus
        1. 7.3.7.1 I2C Bus Protocol
        2. 7.3.7.2 Random Write
        3. 7.3.7.3 Random Read
        4. 7.3.7.4 Sequential Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Control Pins
      2. 7.4.2 EMI Considerations
      3. 7.4.3 Operating Modes and Faults
    5. 7.5 Register Maps
      1. 7.5.1 I2C Address Register Definitions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Amplifier Output Filtering
        2. 8.2.1.2 Amplifier Output Snubbers
        3. 8.2.1.3 Bootstrap Capacitors
        4. 8.2.1.4 Analog Audio Input Filter
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Unused Pin Connections
          1. 8.2.2.1.1 MUTE Pin
          2. 8.2.2.1.2 STANDBY Pin
          3. 8.2.2.1.3 I2C Pins (SDA and SCL)
          4. 8.2.2.1.4 Terminating Unused Outputs
          5. 8.2.2.1.5 Using a Single-Ended Audio Input
      3. 8.2.3 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
      1. 9.2.1 Top Layer
      2. 9.2.2 Second Layer – Signal Layer
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7.2 Random Write

As shown in Figure 7-5, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the internal memory address being accessed. After receiving the address byte, the device again responds with an acknowledge bit. Next, the master device transmits the data byte for writing to the memory address being accessed. After receiving the data byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

GUID-9A07F0EE-D353-4822-A099-31DA44EC8554-low.gifFigure 7-5 Random Write Transfer