SLES217D November   2010  – March 2015 TAS5630B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Characteristics (BTL)
    7. 6.7 Audio Specification (Single-Ended Output)
    8. 6.8 Audio Specification (PBTL)
    9. 6.9 Typical Characteristics
      1. 6.9.1 BTL Configuration
      2. 6.9.2 SE Configuration
      3. 6.9.3 PBTL Configuration
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supplies
      2. 7.3.2  System Power-Up and Power-Down Sequence
        1. 7.3.2.1 Powering Up
        2. 7.3.2.2 Powering Down
      3. 7.3.3  Error Reporting
      4. 7.3.4  Device Protection System
      5. 7.3.5  Pin-to-Pin Short-Circuit Protection (PPSC)
      6. 7.3.6  Overtemperature Protection
      7. 7.3.7  Undervoltage Protection (UVP) and Power-On Reset (POR)
      8. 7.3.8  Device Reset
      9. 7.3.9  Click and Pop in SE-Mode
      10. 7.3.10 PBTL Overload and Short Circuit
      11. 7.3.11 Oscillator
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 PCB Material Recommendation
      2. 8.1.2 PVDD Capacitor Recommendation
      3. 8.1.3 Decoupling Capacitor Recommendations
      4. 8.1.4 System Design Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Schematic
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Differential-Input BTL Application With BD Modulation Filters
      3. 8.2.3 Typical Differential (2N) PBTL Application With BD Modulation Filters
      4. 8.2.4 Typical SE Application
      5. 8.2.5 Typical 2.1 System Differential-Input BTL and Unbalanced-Input SE Application
      6. 8.2.6 Typical Differential-Input BTL Application With BD Modulation Filters, DKD Package
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DKD Package
44 Pins HSSOP
Top View
TAS5630B posdkd_sles217.gif
PHD Package
64 Pins HTQFP
Top View
TAS5630B posphd_sles217.gif
TAS5630B pinphd_sles217.gifFigure 1. Pin One Location PHD Package

Pin Functions

PIN FUNCTION(1) DESCRIPTION
NAME HTQFP HSSOP
AGND 8 10 P Analog ground
BST_A 54 43 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_A required.
BST_B 41 34 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_B required.
BST_C 40 33 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_C required.
BST_D 27 24 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_D required.
CLIP 18 — O Clipping warning; open drain; active-low
C_STARTUP 3 5 O Start-up ramp requires a charging capacitor of 4.7 nF to AGND in BTL mode
FREQ_ADJ 12 14 I PWM frame-rate-programming pin requires resistor to AGND
GND 7, 23, 24, 57, 58 9 P Ground
GND_A 48, 49 38 P Power ground for half-bridge A
GND_B 46, 47 37 P Power ground for half-bridge B
GND_C 34, 35 30 P Power ground for half-bridge C
GND_D 32, 33 29 P Power ground for half-bridge D
GVDD_A 55 — P Gate-drive voltage supply requires 0.1-μF capacitor to GND_A
GVDD_B 56 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_B
GVDD_C 25 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_C
GVDD_D 26 — P Gate drive voltage supply requires 0.1-μF capacitor to GND_D
GVDD_AB — 44 P Gate drive voltage supply requires 0.22-μF capacitor to GND_A/GND_B
GVDD_CD — 23 P Gate drive voltage supply requires 0.22-μF capacitor to GND_C/GND_D
INPUT_A 4 6 I Input signal for half-bridge A
INPUT_B 5 7 I Input signal for half-bridge B
INPUT_C 10 12 I Input signal for half-bridge C
INPUT_D 11 13 I Input signal for half-bridge D
M1 20 20 I Mode selection
M2 21 21 I Mode selection
M3 22 22 I Mode selection
NC 59–62 – — No connect; pins may be grounded.
OC_ADJ 1 3 O Analog overcurrent-programming pin requires resistor to AGND. 64-pin package (PHD) = 22 kΩ. 44-pin PSOP3 (DKD) = 24 kΩ
OSC_IO+ 13 15 I/O Oscillator master/slave output/input
OSC_IO– 14 16 I/O Oscillator master/slave output/input
OTW — 18 O Overtemperature warning signal, open-drain, active-low
OTW1 16 — O Overtemperature warning signal, open-drain, active-low
OTW2 17 — O Overtemperature warning signal, open-drain, active-low
OUT_A 52, 53 39, 40 O Output, half-bridge A
OUT_B 44, 45 36 O Output, half-bridge B
OUT_C 36, 37 31 O Output, half-bridge C
OUT_D 28, 29 27, 28 O Output, half-bridge D
PSU_REF 63 1 P PSU reference requires close decoupling of 330 pF to AGND.
PVDD_A 50, 51 41, 42 P Power-supply input for half-bridge A requires close decoupling of 0.01-μF capacitor in parallel with 2.2-μF capacitor to GND_A.
PVDD_B 42, 43 35 P Power-supply input for half-bridge B requires close decoupling of 0.01-μF capacitor in parallel with 2.2-μF capacitor to GND_B.
PVDD_C 38, 39 32 P Power-supply input for half-bridge C requires close decoupling of 0.0- μF capacitor in parallel with 2.2-μF capacitor to GND_C.
PVDD_D 30, 31 25, 26 P Power-supply input for half-bridge D requires close decoupling of 0.01-μF capacitor in parallel with 2.2-μF capacitor to GND_D.
READY 19 19 O Normal operation; open-drain; active-high
RESET 2 4 I Device reset input; active-low
SD 15 17 O Shutdown signal, open-drain, active-low
VDD 64 2 P Power supply for digital voltage regulator requires a 10-μF capacitor in parallel with a 0.1-μF capacitor to GND for decoupling.
VI_CM 6 8 O Analog comparator reference node requires close decoupling of 1 nF to AGND.
VREG 9 11 P Regulator supply filter pin requires 0.1-μF capacitor to AGND.
(1) I = Input, O = Output, P = Power