SLAS931 October   2017 TAS5634

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Audio Specification Stereo (BTL)
    6. 7.6 Audio Specifications Mono (PBTL)
    7. 7.7 Audio Specification 4 Channels (SE)
    8. 7.8 Electrical Characteristics
    9. 7.9 Typical Characteristics
      1. 7.9.1 BTL Configuration
      2. 7.9.2 PBTL Configuration
      3. 7.9.3 SE Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Closed-Loop Architecture
      2. 8.3.2  Power Supplies
        1. 8.3.2.1 BST, Bootstrap Supply
        2. 8.3.2.2 PVDD, Output Stage Power Supply
        3. 8.3.2.3 GVDD, Gate-Drive Power Supply
        4. 8.3.2.4 VDD Supply, Internal Regulators (DVDD and AVDD)
      3. 8.3.3  System Power-Up / Power-Down Sequence
        1. 8.3.3.1 Powering Up
        2. 8.3.3.2 Powering Down
      4. 8.3.4  Startup and Shutdown Ramp Sequence (C_START)
      5. 8.3.5  Device Protection System
      6. 8.3.6  Overload and Short Circuit Current Protection
      7. 8.3.7  DC Speaker Protection
      8. 8.3.8  Pin-To-Pin Short Circuit Protection (PPSC)
      9. 8.3.9  Overtemperature Protection
      10. 8.3.10 Overtemperature Warning, OTW
      11. 8.3.11 Undervoltage Protection (UVP) and Power-On Reset (POR)
      12. 8.3.12 Error Reporting
      13. 8.3.13 Fault Handling
      14. 8.3.14 System Design Consideration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Stereo, Bridge-tied Load (BTL)
      2. 8.4.2 Mono, Paralleled Bridge-tied Load (PBTL)
      3. 8.4.3 4-Channel, Single-ended (SE)
      4. 8.4.4 BD Modulation
      5. 8.4.5 Device Reset
      6. 8.4.6 Unused Output Channels
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Pin Connections
        4. 9.2.1.4 Application Curves
      2. 9.2.2 Typical PBTL Configuration
        1. 9.2.2.1 Application Curves
      3. 9.2.3 Typical SE Configuration
        1. 9.2.3.1 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
    2. 10.2 Bootstrap Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material Recommendation
      2. 11.1.2 PVDD Capacitor Recommendation
      3. 11.1.3 Decoupling Capacitor Recommendation
      4. 11.1.4 Circuit Component Requirements
      5. 11.1.5 Printed Circuit Board Requirements
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 Power Supplies

To simplify power supply design, the TAS5634 requires only two voltage supplies. A 12-V supply and 58-V (typical) power-stage supply. An internal voltage regulator provides the supply voltage for the digital and low-voltage analog circuitry. Additionally, a floating voltage supply, using the built-in bootstrap circuit, provides the high-side gate drive voltage for each half-bridge.

The PWM signal paths, including gate drive and output stage, are designed as identical, independent half-bridges. Each half-bridge has separate bootstrap pins (BST_X) and each full-bridge has separate power stage supply (PVDD_X) and gate supply (GVDD_X). TI highly recommends separating GVDD_AB, GVDD_CD, and VDD on the printed-circuit-board (PCB) using RC filters (see Layout Example for details). These RC filters provide the recommended high-frequency isolation between GVDD_X and VDD. Place all decoupling capacitors close to the associated pins to avoid stray inductance.

Pay special attention to the power-stage power supply; this includes component selection, PCB placement and routing. For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X connection is decoupled with a minimum of 470-nF ceramic capacitors placed as close as possible to each supply pin. TI recommends following the PCB layout of the TAS5634EVM. For additional information on recommended power supply and required components, see the application diagrams in this data sheet.

The 12-V supply must have low-noise and low-output-impedance from a voltage regulator. Likewise, the 58-V power stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical because of the internal power-on reset circuit. This makes the TAS5634 protected against erroneous power-stage turn on due to parasitic gate charging when power supplies are applied. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).

10.2 Bootstrap Supply

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 300 kHz to 400 kHz, TI recommends using 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.