SLOS989B November   2017  – November 2019 TAS5720A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital I/O Pins
    6. 6.6  Master Clock
    7. 6.7  Serial Audio Port
    8. 6.8  Protection Circuitry
    9. 6.9  Speaker Amplifier in All Modes
    10. 6.10 Speaker Amplifier in All Modes
    11. 6.11 I²C Control Port
    12. 6.12 Typical Idle, Mute, Shutdown, Operational Power Consumption
    13. 6.13 Typical Characteristics (Mono Mode): fSPK_AMP = 384 kHz
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Speaker Amplifier Audio Signal Path
        1. 8.3.2.1 Serial Audio Port (SAP)
          1. 8.3.2.1.1 I²S Timing
          2. 8.3.2.1.2 Left-Justified
          3. 8.3.2.1.3 Right-Justified
        2. 8.3.2.2 DC Blocking Filter
        3. 8.3.2.3 Digital Boost and Volume Control
        4. 8.3.2.4 Digital Clipper
        5. 8.3.2.5 Closed-Loop Class-D Amplifier
      3. 8.3.3 Speaker Amplifier Protection Suite
        1. 8.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 8.3.3.2 DC Detect Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control Mode
        1. 8.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 8.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 8.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 8.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 8.4.1.5 Hardware Control Mode Select (HW/SCL Pin)
        6. 8.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 8.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 8.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 8.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 8.4.2 Software Control Mode
        1. 8.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 8.4.2.2 Serial Audio Port Controls
          1. 8.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 8.4.2.3 Channel Select via Software Control
        4. 8.4.2.4 Speaker Amplifier Gain Structure
          1. 8.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
        5. 8.4.2.5 I²C Software Control Port
          1. 8.4.2.5.1 Setting the I²C Device Address
          2. 8.4.2.5.2 General Operation of the I²C Control Port
          3. 8.4.2.5.3 Writing to the I²C Control Port
          4. 8.4.2.5.4 Reading from the I²C Control Port
    5. 8.5 Register Maps
      1. 8.5.1 Control Port Registers - Quick Reference
      2. 8.5.2 Control Port Registers - Detailed Description
        1. 8.5.2.1  Device Identification Register (0x00)
          1. Table 9. Device Identification Register Field Descriptions
        2. 8.5.2.2  Power Control Register (0x01)
          1. Table 10. Power Control Register Field Descriptions
        3. 8.5.2.3  Digital Control Register (0x02)
          1. Table 11. Digital Control Register Field Descriptions
        4. 8.5.2.4  Volume Control Configuration Register (0x03)
          1. Table 12. Volume Control Configuration Register Field Descriptions
        5. 8.5.2.5  Left Channel Volume Control Register (0x04)
          1. Table 13. Left Channel Volume Control Register Field Descriptions
        6. 8.5.2.6  Right Channel Volume Control Register (0x05)
          1. Table 14. Right Channel Volume Control Register Field Descriptions
        7. 8.5.2.7  Analog Control Register (0x06)
          1. Table 15. Analog Control Register Field Descriptions
        8. 8.5.2.8  Reserved Register (0x07)
        9. 8.5.2.9  Fault Configuration and Error Status Register (0x08)
          1. Table 16. Fault Configuration and Error Status Register Field Descriptions
        10. 8.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 8.5.2.11 Digital Clipper Control 2 Register (0x10)
          1. Table 17. Digital Clipper Control 2 Register Field Descriptions
        12. 8.5.2.12 Digital Clipper Control 1 Register (0x11)
          1. Table 18. Digital Clipper Control 1 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Mono Output Using Software Control
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Startup Procedures- Software Control Mode
          2. 9.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.1.2.3 Component Selection and Hardware Connections
            1. 9.2.1.2.3.1 I²C Pull-Up Resistors
            2. 9.2.1.2.3.2 Digital I/O Connectivity
      2. 9.2.2 Mono Output Using Hardware Control
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.2.2.3 Digital I/O Connectivity
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB Footprint and Via Arrangement
            1. 11.1.3.2.1.1 Solder Stencil
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2.5.3 Writing to the I²C Control Port

As shown in Figure 12, a single-byte data-write transfer begins with the master device transmitting a START condition followed by the I²C and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C and the read/write bit, the TAS5720A-Q1 responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the TAS5720A-Q1 register being accessed. After receiving the address byte, the TAS5720A-Q1 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5720A-Q1 again responds with an acknowledge bit. Finally, the master device transmits a STOP condition to complete the single-byte data-write transfer.

TAS5720A-Q1 t0036-01.gifFigure 12. Write Transfer