SLOS838C July 2013 – August 2015 TAS5731M
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Figure 68, Figure 71, and Figure 72 highlight the required external components and system level connections for proper operation of the device in several popular use cases.
Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes of operation. Any design variation can be supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.
A stereo system generally refers to a system in which there are two full range speakers without a separate amplifier path for the speakers that reproduce the low-frequency content. In this system, two channels are presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two separate speakers.
Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the audio for the left channel and the other channel containing the audio for the right channel.
The Stereo BTL Configuration with Headphone and Line Driver Amplifier application is shown in Figure 68.
SPACE
PARAMETER | EXAMPLE |
---|---|
Low Power Supply | 3.3 V |
High Power Supply | 8 V to 24 V |
Host Processor | I2S Compliant Master |
I2C Compliant Master | |
GPIO Control | |
Output Filters | Inductor-Capacitor Low Pass Filter |
Speaker | 4 Ω minimum |
The typical connections required for proper operation of the device can be found in the TAS5731EVM User’s Guide (SLOU331). The device was tested with this list of components; deviation from this list of typical application components, unless recommended by this document, may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.
Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I2C bus and are considered to be part of the associated passive components for the System Processor. These resistor values must be chosen per the guidance provided in the I2C Specification.
The digital I/O lines of the TAS5731M are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it must be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count.
Use the following sequence to power up and initialize the device: | ||||
1. | Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V. | |||
2. | Initialize digital inputs and PVDD supply as follows: | |||
• | Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RESET = 1, and wait at least another 13.5 ms. | |||
• | Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs. | |||
3. | Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms. | |||
4. | Configure the DAP via I2C, see TAS5731EVM Evaluation Module User's Guide (SLOU331) for typical values. | |||
5. | Configure remaining registers. | |||
6. | Exit shutdown (sequence defined inShutdown Sequence). |
The following are the only events supported during normal operation: | ||||
1. | Writes to master/channel volume registers | |||
2. | Writes to soft-mute register | |||
3. | Enter and exit shutdown (sequence defined in Shutdown Sequence) |
NOTE
Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD power-up ramp (where tstart is specified by register 0x1A).
Enter: | ||||
1. | Write 0x40 to register 0x05. | |||
2. | Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A). | |||
3. | If desired, reconfigure by returning to step 4 of initialization sequence. | |||
Exit: | ||||
1. | Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD power-up ramp). | |||
2. | Wait at least 1 ms + 1.3 × tstart (where tstart is specified by register 0x1A). | |||
3. | Proceed with normal operation. |
Use the following sequence to power down the device and its supplies: | ||||
1. | If time permits, enter shutdown (sequence defined in Shutdown Sequence); else, in case of sudden power loss, assert PDN = 0 and wait at least 2 ms. | |||
2. | Assert RESET = 0. | |||
3. | Drive digital inputs low and ramp down PVDD supply as follows: | |||
• | Drive all digital inputs low after RESET has been low for at least 2 µs. | |||
• | Ramp down PVDD while ensuring that it remains above 8 V until RESET has been low for at least 2 µs. | |||
4. | Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and that it is never more than 2.5 V below the digital inputs. |
space
CURVE TITLE | FIGURE |
---|---|
Output Power vs Supply Voltage (2.0 BTL Mode) With 4ω Load on Typical 2 Layer PCB Device May Be Thermally Limited Above 20 V |
Figure 18 |
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode) | Figure 19 |
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode) | Figure 20 |
Total Harmonic Distortion + Noise vs Output Power (2.0 BTL Mode) | Figure 21 |
Total Harmonic Distortion vs Frequency (2.0 BTL Mode) | Figure 22 |
Total Harmonic Distortion vs Frequency (2.0 BTL Mode) | Figure 23 |
Total Harmonic Distortion vs Frequency (2.0 BTL Mode) | Figure 24 |
Efficiency vs Output Power (2.0 BTL Mode) | Figure 25 |
Crosstalk vs Frequency (2.0 BTL Mode) | Figure 26 |
Crosstalk vs Frequency (2.0 BTL Mode) | Figure 27 |
Crosstalk vs Frequency (2.0 BTL Mode) | Figure 28 |
Crosstalk vs Frequency (2.0 BTL Mode) | Figure 29 |
Power vs Supply Voltage (2.0 BTL Mode) | Figure 30 |
Idle Channel Noise vs Supply Voltage (2.0 BTL Mode) | Figure 31 |
A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5731M device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while the on-resistance is approximately halved.
The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed together and sent through a low-pass filter in order to create a single audio signal which contains the low frequency information of the two channels.
The Mono Parallel Bridge Tied Load application is shown in Figure 71.
SPACE
PARAMETER | EXAMPLE |
---|---|
Low Power Supply | 3.3 V |
High Power Supply | 8 V to 24 V |
Host Processor | I2S Compliant Master |
I2C Compliant Master | |
GPIO Control | |
Output Filters | Inductor-Capacitor Low Pass Filter |
Speaker | 4 Ω minimum |
Refer to Detailed Design Procedure for information.
SPACE
CURVE TITLE | FIGURE |
---|---|
Output Power vs Supply Voltage (PBTL Mode) With 2ω Load on Typical 2 Layer PCB, Device May Be Thermally Limited Above 20 V |
Figure 32 |
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode) | Figure 33 |
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode) | Figure 34 |
Total Harmonic Distortion + Noise vs Output Power (PBTL Mode) | Figure 35 |
Total Harmonic Distortion vs Frequency (PBTL Mode) | Figure 36 |
Total Harmonic Distortion vs Frequency (PBTL Mode) | Figure 37 |
Total Harmonic Distortion vs Frequency (PBTL Mode) | Figure 38 |
Efficiency vs Output Power (PBTL Mode) | Figure 39 |
Efficiency vs Output Power (PBTL Mode) | Figure 40 |
Power vs Supply Voltage (PBTL Mode) | Figure 41 |
Idle Channel Noise vs Supply Voltage (PBTL Mode) | Figure 42 |
A 2.1 system generally refers to a system in which there are two full range speakers with a separate amplifier path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to the amplifier via the digital input signal, these are driven into two single-ended speakers and are mixed into a third channel, conditioned to stream low-frequency content into a differentially connected speaker.
The 2.1 application is shown in Figure 72.
SPACE
PARAMETER | EXAMPLE |
---|---|
Low Power Supply | 3.3 V |
High Power Supply | 8 V to 24 V |
Host Processor | I2S Compliant Master |
I2C Compliant Master | |
GPIO Control | |
Output Filters | Inductor-Capacitor Low Pass Filter |
Speaker | 4 Ω (BTL), 2 Ω (SE) minimum |
Refer to Detailed Design Procedure for information.
SPACE
CURVE TITLE | FIGURE |
---|---|
Output Power vs Supply Voltage (2.1 SE Mode) With 2 × 4ω + 4ω Load on Typical 2 Layer PCB Device May Be Thermally Limited Above 20 V |
Figure 5 |
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode) | Figure 6 |
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode) | Figure 7 |
Total Harmonic Distortion + Noise vs Output Power (2.1 SE Mode) | Figure 8 |
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode) | Figure 9 |
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode) | Figure 10 |
Total Harmonic Distortion + Noise vs Frequency (2.1 SE Mode) | Figure 11 |
Efficiency vs Total Output Power (2.1 SE Mode) | Figure 12 |
Efficiency vs Total Output Power (2.1 SE Mode) | Figure 13 |
Crosstalk vs Frequency (2.1 SE Mode) | Figure 14 |
Crosstalk vs Frequency (2.1 SE Mode) | Figure 15 |
Crosstalk vs Frequency (2.1 SE Mode) | Figure 16 |
Crosstalk vs Frequency (2.1 SE Mode) | Figure 17 |