SLASE77A March   2016  – March 2016 TAS5733L

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Speaker Amplifier Characteristics
    7. 6.7  Protection Characteristics
    8. 6.8  Master Clock Characteristics
    9. 6.9  I²C Interface Timing Requirements
    10. 6.10 Serial Audio Port Timing Requirements
    11. 6.11 Typical Characteristics - Stereo BTL Mode
    12. 6.12 Typical Characteristics - Mono PBTL Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Audio Signal Processing Overview
    4. 7.4 Feature Description
      1. 7.4.1 Clock, Autodetection, and PLL
      2. 7.4.2 PWM Section
      3. 7.4.3 PWM Level Meter
      4. 7.4.4 Automatic Gain Limiter (AGL)
      5. 7.4.5 Fault Indication
      6. 7.4.6 SSTIMER Pin Functionality
      7. 7.4.7 Device Protection System
        1. 7.4.7.1 Overcurrent (OC) Protection With Current Limiting
        2. 7.4.7.2 Overtemperature Protection
        3. 7.4.7.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Serial Audio Port Operating Modes
      2. 7.5.2 Communication Port Operating Modes
      3. 7.5.3 Speaker Amplifier Modes
        1. 7.5.3.1 Stereo Mode
        2. 7.5.3.2 Mono Mode
    6. 7.6 Programming
      1. 7.6.1 I²C Serial Control Interface
        1. 7.6.1.1 General I²C Operation
        2. 7.6.1.2 I²C Slave Address
        3. 7.6.1.3 Single- and Multiple-Byte Transfers
        4. 7.6.1.4 Single-Byte Write
        5. 7.6.1.5 Multiple-Byte Write
        6. 7.6.1.6 Single-Byte Read
        7. 7.6.1.7 Multiple-Byte Read
      2. 7.6.2 Serial Interface Control and Timing
        1. 7.6.2.1 Serial Data Interface
        2. 7.6.2.2 I²S Timing
        3. 7.6.2.3 Left-Justified
        4. 7.6.2.4 Right-Justified
      3. 7.6.3 26-Bit 3.23 Number Format
    7. 7.7 Register Maps
      1. 7.7.1 Register Summary
      2. 7.7.2 Detailed Register Descriptions
        1. 7.7.2.1  Clock Control Register (0x00)
        2. 7.7.2.2  Device ID Register (0x01)
        3. 7.7.2.3  Error Status Register (0x02)
        4. 7.7.2.4  System Control Register 1 (0x03)
        5. 7.7.2.5  Serial Data Interface Register (0x04)
        6. 7.7.2.6  System Control Register 2 (0x05)
        7. 7.7.2.7  Soft Mute Register (0x06)
        8. 7.7.2.8  Volume Registers (0x07, 0x08, 0x09)
        9. 7.7.2.9  Volume Configuration Register (0x0E)
        10. 7.7.2.10 Modulation Limit Register (0x10)
        11. 7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. 7.7.2.12 PWM Shutdown Group Register (0x19)
        13. 7.7.2.13 Start/Stop Period Register (0x1A)
        14. 7.7.2.14 Oscillator Trim Register (0x1B)
        15. 7.7.2.15 BKND_ERR Register (0x1C)
        16. 7.7.2.16 Input Multiplexer Register (0x20)
        17. 7.7.2.17 PWM Output MUX Register (0x25)
        18. 7.7.2.18 AGL Control Register (0x46)
        19. 7.7.2.19 PWM Switching Rate Control Register (0x4F)
        20. 7.7.2.20 Bank Switch and EQ Control (0x50)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
        1. 8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
        2. 8.1.1.2 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Bridge Tied Load Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Component Selection and Hardware Connections
          2. 8.2.1.2.2 Control and Software Integration
          3. 8.2.1.2.3 I²C Pullup Resistors
          4. 8.2.1.2.4 Digital I/O Connectivity
          5. 8.2.1.2.5 Recommended Startup and Shutdown Procedures
            1. 8.2.1.2.5.1 Start-Up Sequence
            2. 8.2.1.2.5.2 Normal Operation
            3. 8.2.1.2.5.3 Shutdown Sequence
            4. 8.2.1.2.5.4 Power-Down Sequence
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Mono Parallel Bridge Tied Load Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Decoupling Capacitors
      2. 10.1.2 Thermal Performance and Grounding
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

As mentioned previously, the TAS5733L device can be used in stereo and mono mode. This section describes the information required to configure the device for several popular configurations and for integrating the TAS5733L device into the larger system.

8.1.1 External Component Selection Criteria

The Supporting Component Requirements table in each application description section lists the details of the supporting required components in each of the System Application Schematics. Where possible, the supporting component requirements have been consolidated to minimize the number of unique components which are used in the design. Component list consolidation is a method to reduce the number of unique part numbers in a design. Consolidation is done to ease inventory management and reduce the manufacturing steps during board assembly. For this reason, some capacitors are specified at a higher voltage than what would normally be required. An example of this is a 50-V capacitor can be used for decoupling of a 3.3-V power supply net.

In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of that value into a single component type. Similarly, several unique resistors, all having the same size and value but different power ratings can be consolidated by using the highest rated power resistor for each instance of that resistor value.

While this consolidation can seem excessive, the benefits of having fewer components in the design can far outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of the capacitors should be 1.5 times to 1.75 times the power dissipated in the capacitors during normal use case.

8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing

Because the layout is important to the overall performance of the circuit, the package size of the components shown in the component list were intentionally chosen to allow for proper board layout, component placement, and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane extends from the TAS5733L device between two pads of a surface mount component and into to the surrounding copper for increased heat-sinking of the device. While components can be offered in smaller or larger package sizes, the package size should remain identical to that used in the application circuit as shown. This consistency ensures that the layout and routing can be matched very closely, optimizing thermal, electromagnetic, and audio performance of the TAS5733L device in circuit in the final system.

8.1.1.2 Amplifier Output Filtering

The TAS5733L device is often used with a low-pass filter, which is used to filter out the carrier frequency of the PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive element L and a capacitive element C to make up the 2-pole filter. The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several system level constraints. In some low-power use cases that do not have other circuits which are sensitive to EMI, a simple ferrite bead or ferrite bead and capacitor can replace the traditional large inductor and capacitor that are commonly used. In other high-power applications, large toroid inductors are required for maximum power and film capacitors can be preferred due to audio characteristics. Refer to the application report Class-D Filter Design (SLOA119) for a detailed description of proper component selection and design of an L-C filter based upon the desired load and response.

8.2 Typical Applications

These typical connection diagrams highlight the required external components and system level connections for proper operation of the device in several popular use cases. Each of these configurations can be realized using the Evaluation Module (EVM) for the device. These flexible modules allow full evaluation of the device in the most common modes of operation. Any design variation can be supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.

8.2.1 Stereo Bridge Tied Load Application

A stereo system generally refers to a system inside which are two full range speakers without a separate amplifier path for the speakers that reproduce the low-frequency content. In this system, two channels are presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two separate speakers.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the audio for the left channel and the other channel containing the audio for the right channel. While the two channels can contain any two audio channels, such as two surround channels of a multi-channel speaker system, the most popular occurrence in two channels systems is a stereo pair.

The Stereo BTL Configuration is shown in Figure 49.

Figure 49. Stereo Bridge Tied Load Application

8.2.1.1 Design Requirements

The design requirements for the Stereo Bridge Tied Load Application of the TAS5733L device is found in Table 25

Table 25. Design Requirements for Stereo Bridge Tied Load Application

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 8 V to 15 V
Digital I²S Compliant Master
I²C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter (1)
Speaker 4 Ω minimum.
(1) Refer to SLOA119 for a detailed description on the filter design.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Component Selection and Hardware Connections

The typical connections required for proper operation of the device can be found on the TAS5733L User’s Guide. The device was tested with this list of components, deviation from this typical application components unless recommended by this document can produce unwanted results, which could range from degradation of audio performance to destructive failure of the device. The application report Class-D Filter Design (SLOA119) offers a detailed description of proper component selection and design of the output filter based upon the modulation used, desired load and response.

8.2.1.2.2 Control and Software Integration

The TAS5733L device has a bidirectional I²C used to program the registers of the device and to read device status. The TAS5733LEVM and the PurePath Console GUI are powerful tools that allow the TAS5733L evaluation, control and configuration. The Register Dump feature of the PurePath Console software can be used to generate a custom configuration file for any end-system operating mode. Prior approval is required to download PurePath Console GUI. Please request access at http://www.ti.com/tool/purepathconsole.

8.2.1.2.3 I²C Pullup Resistors

Customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.

8.2.1.2.4 Digital I/O Connectivity

The digital I/O lines of the TAS5733L are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pull-up resistor to control the slew rate of the voltage presented to the digital I/O pins. However, having a separate pull-up resistor for each static digital I/O line is not necessary. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count.

8.2.1.2.5 Recommended Startup and Shutdown Procedures

TAS5733L tas5733m_power_sequence_slase77.gif Figure 50. Recommended Start-Up and Shutdown Sequence

8.2.1.2.5.1 Start-Up Sequence

Use the following sequence to power up and initialize the device:

  1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V.
  2. Initialize digital inputs and PVDD supply as follows:
    • Drive RST = 0, PDN = 1, and other digital inputs to their desired state. Wait at least 100 µs, drive RST high
    • Wait ≥ 13.5 ms.
    • Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after AVDD/DVDD reaches 3 V.
    • Wait ≥ 10 µs.
  3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms.
  4. Configure the Digital Audio Processor of the Amplifier via I²C, refer to Section 8.5 Register Maps for more information.
  5. Configure remaining registers.
  6. Exit shutdown (sequence defined in Shutdown Sequence).

8.2.1.2.5.2 Normal Operation

The following are the only events supported during normal operation:

  1. Writes to master/channel volume registers.
  2. Writes to soft-mute register.
  3. Enter and exit shutdown (sequence defined in Shutdown Sequence).

NOTE

Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD power-up ramp (where tstart is specified by register 0x1A).

8.2.1.2.5.3 Shutdown Sequence

Enter:

  1. Write 0x40 to register 0x05.
  2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A).
  3. If desired, reconfigure by returning to step 4 of initialization sequence.

Exit:

  1. Write 0x00 to register 0x05 (exit shutdown command can not be serviced for as much as 240 ms after trim following AVDD/DVDD power-up ramp).
  2. Wait at least 1 ms + 1.3 × tstart (where tstart is specified by register 0x1A).
  3. Proceed with normal operation.

8.2.1.2.5.4 Power-Down Sequence

Use the following sequence to power down the device and its supplies:

  1. If time permits, enter shutdown (sequence defined in Shutdown Sequence); else, in case of sudden power loss, assert PDN = 0 and wait at least 2 ms.
  2. Assert RST = 0.
  3. Drive digital inputs low and ramp down PVDD supply as follows:
    • Drive all digital inputs low after RST has been low for at least 2 µs.
    • Ramp down PVDD while ensuring that it remains above 8 V until RST has been low for at least 2 µs.
  4. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V.

8.2.1.3 Application Performance Plots

CURVE TITLE FIGURE
Output Power Vs Supply Voltage Stereo BTL Mode Figure 5
Total Harmonic Distortion + Noise Vs Output Power Stereo BTL Mode Figure 10
Total Harmonic Distortion + Noise Vs Frequency Stereo BTL Mode Figure 7
Power Efficiency Vs Output Power Stereo BTL Mode Figure 13
Crosstalk Vs Frequency Stereo BTL Mode Figure 15

8.2.2 Mono Parallel Bridge Tied Load Application

A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the loudspeaker simultaneously using an identical audio signal. The primary benefit of operating this device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while the on-resistance is approximately halved.

The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed together and sent through a low-pass filter to create a single audio signal which contains the low-frequency information of the two channels.

The Mono PBTL Configuration is shown in Figure 51.

Figure 51. Mono Parallel Bridge Tied Load Application

8.2.2.1 Design Requirements

The design requirements for the Mono Parallel Bridge Tied Load Appliction of the TAS5733L device is found in Table 26

Table 26. Design Requirements for Mono Parallel Bridge Tied Load Application

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 8 V to 15 V
Digital I²S Compliant Master
I²C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter (1)
Speaker 2 Ω minimum.
(1) Refer to the application report Class-D Filter Design (SLOA119) for a detailed description on the filter design.

8.2.2.2 Detailed Design Procedure

Refer to the Detailed Design Procedure section.

8.2.2.3 Application Performance Plots

CURVE TITLE FIGURE
Output Power Vs Supply Voltage Mono PBTL Mode Figure 23
Total Harmonic Distortion + Noise Vs Output Power Mono PBTL Mode Figure 20
Total Harmonic Distortion + Noise Vs Frequency Mono PBTL Mode Figure 17
Power Efficiency Vs Output Power Mono PBTL Mode Figure 24