SLASEC1B March   2016  – May 2018 TAS5751M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Power vs PVDD
      2.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Speaker Amplifier Characteristics
    7. 6.7  Protection Characteristics
    8. 6.8  Master Clock Characteristics
    9. 6.9  I²C Interface Timing Requirements
    10. 6.10 Serial Audio Port Timing Requirements
    11. 6.11 Typical Characteristics
      1. 6.11.1 Typical Characteristics - Stereo BTL Mode
      2. 6.11.2 Typical Characteristics - Mono PBTL Mode
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Audio Signal Processing Overview
    4. 7.4 Feature Description
      1. 7.4.1 Clock, Autodetection, and PLL
      2. 7.4.2 PWM Section
      3. 7.4.3 PWM Level Meter
      4. 7.4.4 Automatic Gain Limiter (AGL)
      5. 7.4.5 Headphone/Line Amplifier
      6. 7.4.6 Fault Indication
      7. 7.4.7 SSTIMER Pin Functionality
      8. 7.4.8 Device Protection System
        1. 7.4.8.1 Overcurrent (OC) Protection With Current Limiting
        2. 7.4.8.2 Overtemperature Protection
        3. 7.4.8.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Serial Audio Port Operating Modes
      2. 7.5.2 Communication Port Operating Modes
      3. 7.5.3 Speaker Amplifier Modes
        1. 7.5.3.1 Stereo Mode
        2. 7.5.3.2 Mono Mode
    6. 7.6 Programming
      1. 7.6.1 I²C Serial Control Interface
        1. 7.6.1.1 General I²C Operation
        2. 7.6.1.2 I²C Slave Address
          1. 7.6.1.2.1 I²C Device Address Change Procedure
        3. 7.6.1.3 Single- and Multiple-Byte Transfers
        4. 7.6.1.4 Single-Byte Write
        5. 7.6.1.5 Multiple-Byte Write
        6. 7.6.1.6 Single-Byte Read
        7. 7.6.1.7 Multiple-Byte Read
      2. 7.6.2 Serial Interface Control and Timing
        1. 7.6.2.1 Serial Data Interface
        2. 7.6.2.2 I²S Timing
        3. 7.6.2.3 Left-Justified
        4. 7.6.2.4 Right-Justified
      3. 7.6.3 26-Bit 3.23 Number Format
    7. 7.7 Register Maps
      1. 7.7.1 Register Summary
      2. 7.7.2 Detailed Register Descriptions
        1. 7.7.2.1  Clock Control Register (0x00)
        2. 7.7.2.2  Device ID Register (0x01)
        3. 7.7.2.3  Error Status Register (0x02)
        4. 7.7.2.4  System Control Register 1 (0x03)
        5. 7.7.2.5  Serial Data Interface Register (0x04)
        6. 7.7.2.6  System Control Register 2 (0x05)
        7. 7.7.2.7  Soft Mute Register (0x06)
        8. 7.7.2.8  Volume Registers (0x07, 0x08, 0x09)
        9. 7.7.2.9  Volume Configuration Register (0x0E)
        10. 7.7.2.10 Modulation Limit Register (0x10)
        11. 7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. 7.7.2.12 PWM Shutdown Group Register (0x19)
        13. 7.7.2.13 Start/Stop Period Register (0x1A)
        14. 7.7.2.14 Oscillator Trim Register (0x1B)
        15. 7.7.2.15 BKND_ERR Register (0x1C)
        16. 7.7.2.16 Input Multiplexer Register (0x20)
        17. 7.7.2.17 PWM Output MUX Register (0x25)
        18. 7.7.2.18 AGL Control Register (0x46)
        19. 7.7.2.19 PWM Switching Rate Control Register (0x4F)
        20. 7.7.2.20 Bank Switch and EQ Control (0x50)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
        1. 8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
        2. 8.1.1.2 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Bridge Tied Load Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Component Selection and Hardware Connections
          2. 8.2.1.2.2 Control and Software Integration
          3. 8.2.1.2.3 I²C Pullup Resistors
          4. 8.2.1.2.4 Digital I/O Connectivity
          5. 8.2.1.2.5 Recommended Startup and Shutdown Procedures
            1. 8.2.1.2.5.1 Start-Up Sequence
            2. 8.2.1.2.5.2 Normal Operation
            3. 8.2.1.2.5.3 Shutdown Sequence
            4. 8.2.1.2.5.4 Power-Down Sequence
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Mono Parallel Bridge Tied Load Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Decoupling Capacitors
      2. 10.1.2 Thermal Performance and Grounding
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.11.1 Typical Characteristics - Stereo BTL Mode

TAS5751M power_vs_pvdd_slasec1.gifFigure 5. Output Power vs Supply Voltage
TAS5751M G005_THDvFreq12V8R.pngFigure 7. THD+N vs Frequency
TAS5751M G004_THDvFreq12V4R.pngFigure 9. THD+N vs Frequency
TAS5751M G007_THDvFreq18V6R.pngFigure 11. THD+N vs Frequency
TAS5751M G011_THDvFreq24V8R.pngFigure 13. THD+N vs Frequency
TAS5751M G009_THDvFreq24V4R.pngFigure 15. THD+N vs Frequency
TAS5751M G014_THDvPo20Hz1kHz6kHz12V6R.pngFigure 17. THD+N vs Output Power
TAS5751M G018_THDvPo20Hz1kHz6kHz18V8R.pngFigure 19. THD+N vs Output Power
TAS5751M G016_THDvPo20Hz1kHz6kHz18V4R.pngFigure 21. THD+N vs Output Power
TAS5751M G020_THDvPo20Hz1kHz6kHz24V6R.pngFigure 23. THD+N vs Output Power
TAS5751M G023_EffvPo12V18V24V8R.png
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.
Figure 25. Efficiency vs Total Output Power
TAS5751M G025_XtalkvFreq12V8R.pngFigure 27. Crosstalk vs Frequency
TAS5751M G027_XtalkvFreq18V8R.pngFigure 29. Crosstalk vs Frequency
TAS5751M G029_XtalkvFreq24V8R.pngFigure 31. Crosstalk vs Frequency
TAS5751M G012_PVDDvICN8Vto24V8R.pngFigure 6. Idle Channel Noise vs Supply Voltage
TAS5751M G003_THDvFreq12V6R.pngFigure 8. THD+N vs Frequency
TAS5751M G008_THDvFreq18V8R.pngFigure 10. THD+N vs Frequency
TAS5751M G006_THDvFreq18V4R.pngFigure 12. THD+N vs Frequency
TAS5751M G010_THDvFreq24V6R.pngFigure 14. THD+N vs Frequency
TAS5751M G015_THDvPo20Hz1kHz6kHz12V8R.pngFigure 16. THD+N vs Output Power
TAS5751M G013_THDvPo20Hz1kHz6kHz12V4R.pngFigure 18. THD+N vs Output Power
TAS5751M G017_THDvPo20Hz1kHz6kHz18V6R.pngFigure 20. THD+N vs Output Power
TAS5751M G021_THDvPo20Hz1kHz6kHz24V8R.pngFigure 22. THD+N vs Output Power
TAS5751M G019_THDvPo20Hz1kHz6kHz24V4R.pngFigure 24. THD+N vs Output Power
TAS5751M G022_EffvPo12V18V24V4R.png
Total Output Power includes power delivered from both amplifier outputs. For instance, 40 W of total output power means 2 × 20 W, with 20 W delivered by one channel and 20 W delivered by the other channel.
Figure 26. Efficiency vs Total Output Power
TAS5751M G024_XtalkvFreq12V4R.pngFigure 28. Crosstalk vs Frequency
TAS5751M G026_XtalkvFreq18V4R.pngFigure 30. Crosstalk vs Frequency
TAS5751M G028_XtalkvFreq24V4R.pngFigure 32. Crosstalk vs Frequency