The TAS5760LD is a stereo I2S input device which includes hardware and software (I²C) control modes, integrated digital clipper, several gain options, and a wide power supply operating range to enable use in a multitude of applications. The TAS5760LD operates with a nominal supply voltage from 4.5 to 15 VDC. The device has an integrated DirectPath™ headphone amplifier and line driver to increase system level integration and reduce total solution costs.
An optimal mix of thermal performance and device cost is provided in the 120-mΩ RDS(ON) of the output MOSFETs. Additionally, a thermally enhanced 48-Pin TSSOP provides excellent operation in the elevated ambient temperatures found in modern consumer electronic devices.
The entire TAS5760xx family is pin-to-pin compatible in the 48-Pin TSSOP package. Alternatively, to achieve the smallest possible solutions size for applications where pin-to-pin compatibility and a headphone or line driver are not required, a 32-Pin TSSOP package is offered for the TAS5760M and TAS5760L devices. The I2C register map in all of the TAS5760xx devices are identical, to ensure low development overhead when choosing between devices based upon system-level requirements.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TAS5760LD | HTSSOP (48) | 12.50 mm × 6.10 mm |
NOTE:
Thermal Limits were determined via the TAS5760xxEVMChanges from B Revision (May 2017) to C Revision
Changes from A Revision (July 2015) to B Revision
Changes from * Revision (July 2013) to A Revision
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | 4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | 1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
TA | Ambient Operating Temperature | –25 | 85 | °C | |
AVDD | AVDD Supply | 4.5 | 16.5 | V | |
PVDD | PVDD Supply | 4.5 | 16.5 | V | |
DRVDD, DVDD | DRVDD and DVDD Supply | 2.8 | 3.63 | V | |
VIH(DR) | Input Logic HIGH for DVDD and DRVDD Referenced Digital Inputs | DVDD | V | ||
VIL(DR) | Input Logic LOW for DVDD and DRVDD Referenced Digital Inputs | 0 | V | ||
RHP | Headphone Load | 16 | Ω | ||
RLD | Line Driver Load | 1 | Ω | ||
RSPK (BTL) | Minimum Speaker Load in BTL Mode | 4 | Ω | ||
RSPK (PBTL) | Minimum Speaker Load in PBTL Mode | 2 | Ω |
THERMAL METRIC(1) | TAS5760LD | UNIT | ||
---|---|---|---|---|
DCA [HTSSOP] | DCA [HTSSOP] | |||
48 PIN(2) | 48 PIN(3) | |||
θJA | Junction-to-ambient thermal resistance | 60.3 | 30.2 | °C/W |
θJC(top) | Junction-to-case (top) thermal resistance | 16 | 14.3 | °C/W |
θJB | Junction-to-board thermal resistance | 12 | 12.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 11.9 | 12.7 | °C/W |
θJC(bottom) | Junction-to-case (bottom) thermal resistance | 0.8 | 0.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
DSCLK | Allowable SCLK Duty Cycle | 45% | 50% | 55% | ||
tH_L | Time high and low, SCLK, LRCK, SDIN | 10 | ns | |||
tSU
tHLD |
Setup and Hold time. LRCK, SDIN input to SCLK edge | Input tRISE ≤ 1 ns, input tFALL ≤ 1 ns | 5 | ns | ||
Input tRISE ≤ 4 ns, input tFALL ≤ 4 ns | 8 | |||||
Input tRISE ≤ 8 ns, input tFALL ≤ 8 ns | 12 | |||||
tRISE | Rise-time SCLK, LRCK, SDIN inputs | 8 | ns | |||
tFALL | Fall-time SCLK, LRCK, SDIN inputs | 8 | ns | |||
fS | Supported Input Sample Rates | Sample rates above 48kHz supported by "double speed mode," which is activated through the I²C control port | 32 | 96 | kHz | |
fSCLK | Supported SCLK Frequencies | Values include: 32, 48, 64 | 32 | 64 | fS |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OVERTHRES(PVDD) | PVDD Overvoltage Error Threshold | PVDD Rising | 18 | V | ||
OVEFTHRES(PVDD) | PVDD Overvoltage Error Threshold | PVDD Falling | 17.3 | V | ||
UVEFTHRES(PVDD) | PVDD Undervoltage Error (UVE) Threshold | PVDD Falling | 3.95 | V | ||
UVERTHRES(PVDD) | PVDD UVE Threshold (PVDD Rising) | PVDD Rising | 4.15 | V | ||
OTETHRES | Overtemperature Error (OTE) Threshold | 150 | °C | |||
OTEHYST | Overtemperature Error (OTE) Hysteresis | 15 | °C | |||
OCETHRES | Overcurrent Error (OCE) Threshold for each BTL Output | PVDD= 15V, TA = 25 °C | 7 | A | ||
DCETHRES | DC Error (DCE) Threshold | PVDD= 12V, TA = 25 °C | 2.6 | V | ||
TSPK_FAULT | Speaker Amplifier Fault Time Out period | DC Detect Error | 650 | ms | ||
OTE or OCP Fault | 1.3 | s | ||||
UVETHRES(DRVDD) | Undervoltage Error (UVE) Threshold for headphone and line driver amplifier | Sensed on DR_UVE pin | 1.25 | V | ||
ILIMIT(DR) | Current Sourcing Limit of the Headphone and line driver amplifier | 68 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
AV00 | Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 00 | Hardware Control Mode (Additional gain settings available in Software Control Mode)(1) | 25.2 | dBV | ||
AV01 | Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 01 | Hardware Control Mode (Additional gain settings available in Software Control Mode)(1) | 28.6 | dBV | ||
AV10 | Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 10 | Hardware Control Mode (Additional gain settings available in Software Control Mode)(1) | 31 | dBV | ||
AV11 | Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 11 | (This setting places the device in Software Control Mode) | (Set via I²C) | |||
|VOS|(SPK_AMP) | Speaker Amplifier DC Offset | BTL, Worst case over voltage, gain settings | 10 | mV | ||
PBTL, Worst case over voltage, gain settings | 15 | mV | ||||
fSPK_AMP(0) | Speaker Amplifier Switching Frequency when PWM_FREQ Pin = 0 | (Hardware Control Mode. Additional switching rates available in Software Control Mode.) | 16 | fS | ||
fSPK_AMP(1) | Speaker Amplifier Switching Frequency when PWM_FREQ Pin = 1 | (Hardware Control Mode. Additional switching rates available in Software Control Mode.) | 8 | fS | ||
RDS(ON) | On Resistance of Output MOSFET (both high-side and low-side) | PVDD = 15 V, TA = 25 °C, Die Only | 120 | mΩ | ||
PVDD= 15V, TA = 25 °C, Includes: Die, Bond Wires, Leadframe | 150 | mΩ | ||||
fC | –3-dB Corner Frequency of High-Pass Filter | fS = 44.1 kHz | 3.7 | Hz | ||
fS = 48 kHz | 4 | |||||
fS = 88.2 kHz | 7.4 | |||||
fS = 96 kHz | 8 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ICN(SPK) | Idle Channel Noise | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, A-Weighted |
- | 66 | - | µVrms |
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, A-Weighted |
- | 75 | - | µVrms | ||
PO(SPK) | Maximum Instantaneous Output Power Per. Ch. | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, |
- | 14.2 | - | W |
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% |
- | 8 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, |
- | 21.9 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% |
- | 12.5 | - | W | ||
PO(SPK) | Maximum Continuous Output Power Per. Ch.(1) | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, |
- | 14 | - | W |
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% |
- | 8 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, |
- | 13.25 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% |
- | 12.5 | - | W | ||
SNR(SPK) | Signal to Noise Ratio (Referenced to THD+N = 1%) | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, A-Weighted, -60dBFS Input |
- | 99.7 | - | dB |
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, A-Weighted, -60dBFS Input |
- | 98.2 | - | dB | ||
THD+N(SPK) | Total Harmonic Distortion and Noise | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, Po = 1 W |
- | 0.02% | - | |
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, Po = 1 W |
- | 0.03% | - | |||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, Po = 1 W |
- | 0.03% | - | |||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, Po = 1 W |
- | 0.03% | - | |||
X-Talk(SPK) | Cross-talk (worst case between LtoR and RtoL coupling) | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, Input Signal 250 mVrms, 1kHz Sine |
- | -92 | - | dB |
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, Input Signal 250 mVrms, 1kHz Sine |
- | -93 | - | dB |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ICN | Idle Channel Noise | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, A-Weighted |
- | 69 | - | µVrms |
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, A-Weighted |
- | 85 | - | µVrms | ||
PO(SPK) | Maximum Instantaneous Output Power | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 2Ω, THD+N = 0.1%, |
- | 28.6 | - | W |
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, |
- | 15.9 | - | W | ||
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% |
- | 8.4 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, THD+N = 0.1%, |
- | 43.2 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, |
- | 25 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% |
- | 13.3 | - | W | ||
PO(SPK) | Maximum Continuous Output Power(1) | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 2Ω, THD+N = 0.1%, |
- | 30 | - | W |
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, THD+N = 0.1%, |
- | 15.9 | - | W | ||
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, THD+N = 0.1% |
- | 8.4 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, THD+N = 0.1%, |
- | 28.5 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, THD+N = 0.1%, |
- | 25 | - | W | ||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, THD+N = 0.1% |
- | 13.3 | - | W | ||
SNR | Signal to Noise Ratio (Referenced to THD+N = 1%) | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, A-Weighted, -60dBFS Input |
- | 100.4 | - | dB |
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, A-Weighted, -60dBFS Input |
- | 99.5 | - | dB | ||
THD+N(SPK) | Total Harmonic Distortion and Noise | PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 2Ω, Po = 1 W |
- | 0.03% | - | |
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 4Ω, Po = 1 W |
- | 0.02% | - | |||
PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, RSPK = 8Ω, Po = 1 W |
- | 0.02% | - | |||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 2Ω, Po = 1 W |
- | 0.03% | - | |||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 4Ω, Po = 1 W |
- | 0.02% | - | |||
PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, RSPK = 8Ω, Po = 1 W |
- | 0.02% | - |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Input to Output Attenuation when muted | 80 | dB | ||||
|VOS|(DR) | Output Offset Voltage of Headphone Amplifier and Line Driver | 0.5 | mV | |||
fCP | Charge Pump Switching Frequency | 200 | 300 | 400 | kHz | |
ICN(HP) | Idle Channel Noise | R(HP) = 32 Ω, A-Weighted | 13 | µVrms | ||
ICN(LD) | Idle Channel Noise | R(LD) = 3 kΩ, A-Weighted | 11 | µVrms | ||
Po(HP) | Headphone Amplifier Output Power | R(HP) = 16 Ω, THD+N = 1%, Outputs in Phase | 40 | mW | ||
PSRR(DR) | Power Supply Rejection Ratio of Headphone Amplifier and Line Driver | 80 | dB | |||
SNR(HP) | Signal to Noise Ratio | (Referenced to 25 mW Output Signal), R(HP) = 16 Ω, A-Weighted | 96 | dB | ||
SNR(LD) | Signal to Noise Ratio | (Referenced to 2 Vrms Output Signal), R(LD) = 3 kΩ, A-Weighted | 90 | 105 | dB | |
THD+N(HP) | Total Harmonic Distortion and Noise for the Headphone Amplifier | PO(HP) = 10 mW | 0.01% | |||
THD+N(LD) | Total Harmonic Distortion and Noise for the Line Driver | VO(LD) = 2 Vrms | 0.002% | |||
Vo(LD) | Line Driver Output Voltage | THD+N = 1%, R(LD) = 3kΩ, Outputs in Phase | 2 | 2.4 | Vrms | |
X-Talk(HP) | Cross-talk (worst case between LtoR and RtoL coupling) | PO(HP) = 20 mW | –90 | dB | ||
X-Talk(LD) | Cross-talk (worst case between LtoR and RtoL coupling) | Vo = 1 Vrms | –111 | dB | ||
ZO(DR) | Output Impedance when muted | DR_MUTE = LOW | 110 | mΩ | ||
IMUTE(DR) | Current drawn from DRVDD supply in mute | DR_MUTE = LOW | 12 | mA | ||
IDRVDD(HP) | Current drawn from DRVDD supply with headphone | DR_MUTE = HIGH, PO(HP) = 25 mW, Input = 1kHz | 60 | mA | ||
IDRVDD(LD) | Current drawn from DRVDD supply with line driver | DR_MUTE = HIGH, VO(LD) = 2 Vrms, Input = 1kHz | 12 | mA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CL(I²C) | Allowable Load Capacitance for Each I²C Line | 400 | pF | |||
fSCL | Support SCL frequency | No Wait States | 400 | kHz | ||
tbuf | Bus Free time between STOP and START conditions | 1.3 | µS | |||
tf(I²C) | Rise Time, SCL and SDA | 300 | ns | |||
th1(I²C) | Hold Time, SCL to SDA | 0 | ns | |||
th2(I²C) | Hold Time, START condition to SCL | 0.6 | µs | |||
tI²C(start) | I²C Startup Time | 12 | mS | |||
tr(I²C) | Rise Time, SCL and SDA | 300 | ns | |||
tsu1(I²C) | Setup Time, SDA to SCL | 100 | ns | |||
tsu2(I²C) | Setup Time, SCL to START condition | 0.6 | µS | |||
tsu3(I²C) | Setup Time, SCL to STOP condition | 0.6 | µS | |||
Tw(H) | Required Pulse Duration, SCL HIGH | 0.6 | µS | |||
Tw(L) | Required Pulse Duration, SCL LOW | 1.3 | µS |
VPVDD
[V] |
RSPK
[Ω] |
SPEAKER AMPLIFIER STATE | IPVDD+AVDD
[mA] |
IDVDD
[mA] |
PDISS
[W] |
|
---|---|---|---|---|---|---|
6 | 4 | fSPK_AMP = 384kHz | Idle | 23.48 | 3.73 | 0.15 |
8 | 23.44 | 3.72 | 0.15 | |||
4 | Mute | 23.53 | 3.72 | 0.15 | ||
8 | 23.46 | 3.72 | 0.15 | |||
4 | Sleep | 13.26 | 0.48 | 0.08 | ||
8 | 13.27 | 0.53 | 0.08 | |||
4 | Shutdown | 0.046 | 0.04 | 0 | ||
8 | 0.046 | 0.03 | 0 | |||
4 | fSPK_AMP = 768kHz | Idle | 30.94 | 3.71 | 0.2 | |
8 | 30.94 | 3.71 | 0.2 | |||
4 | Mute | 29.37 | 3.71 | 0.19 | ||
8 | 29.39 | 3.71 | 0.19 | |||
4 | Sleep | 13.24 | 0.5 | 0.08 | ||
8 | 13.23 | 0.52 | 0.08 | |||
4 | Shutdown | 0.046 | 0.03 | 0 | ||
8 | 0.046 | 0.03 | 0 | |||
4 | fSPK_AMP = 1152kHz | Idle | 39.39 | 3.7 | 0.25 | |
8 | 39.43 | 3.7 | 0.25 | |||
4 | Mute | 36.91 | 3.7 | 0.23 | ||
8 | 36.9 | 3.69 | 0.23 | |||
4 | Sleep | 13.17 | 0.53 | 0.08 | ||
8 | 13.13 | 0.45 | 0.08 | |||
4 | Shutdown | 0.046 | 0.03 | 0 | ||
8 | 0.046 | 0.03 | 0 | |||
12 | 4 | fSPK_AMP = 384kHz | Idle | 32.95 | 3.74 | 0.41 |
8 | 32.93 | 3.73 | 0.41 | |||
4 | Mute | 32.98 | 3.73 | 0.41 | ||
8 | 32.97 | 3.73 | 0.41 | |||
4 | Sleep | 12.71 | 0.47 | 0.15 | ||
8 | 12.75 | 0.5 | 0.15 | |||
4 | Shutdown | 0.053 | 0.04 | 0 | ||
8 | 0.053 | 0.04 | 0 | |||
4 | fSPK_AMP = 768kHz | Idle | 44.84 | 3.73 | 0.55 | |
8 | 44.82 | 3.73 | 0.55 | |||
4 | Mute | 42.71 | 3.72 | 0.52 | ||
8 | 42.66 | 3.72 | 0.52 | |||
4 | Sleep | 12.71 | 0.49 | 0.15 | ||
8 | 12.73 | 0.52 | 0.15 | |||
4 | Shutdown | 0.063 | 0.03 | 0 | ||
8 | 0.053 | 0.03 | 0 | |||
4 | fSPK_AMP = 1152kHz | Idle | 59.3 | 3.73 | 0.72 | |
8 | 59.3 | 3.73 | 0.72 | |||
4 | Mute | 55.74 | 3.72 | 0.68 | ||
8 | 55.74 | 3.72 | 0.68 | |||
4 | Sleep | 12.67 | 0.49 | 0.15 | ||
8 | 12.61 | 0.43 | 0.15 | |||
4 | Shutdown | 0.053 | 0.02 | 0 | ||
8 | 0.053 | 0.03 | 0 |
All parameters are measured according to the conditions described in Specifications.
The TAS5760LD is a flexible and easy-to-use stereo class-D speaker amplifier with an I²S input serial audio port. The TAS5760LD device also includes a dual-purpose headphone and line driver, which features pop/click-less operation, great audio performance, variable gain setting, and minimal bill of materials. The TAS5760LD supports a variety of audio clock configurations via two speed modes. In Hardware Control mode, the device only operates in single-speed mode. When used in Software Control mode, the device can be placed into double speed mode to support higher sample rates, such as 88.2 kHz and 96 kHz. The outputs of the TAS5760LD can be configured to drive two speakers in stereo Bridge Tied Load (BTL) mode or a single speaker in Parallel Bridge Tied Load (PBTL) mode.
Only two power supplies are required for the TAS5760LD. They are a 3.3-V power supply, called VDD, for the small signal analog and digital and a higher voltage power supply, called PVDD, for the output stage of the speaker amplifier. To enable use in a variety of applications, PVDD can be operated over a large range of voltages, as specified in the Recommended Operating Conditions.
To configure and control the TAS5760LD, two methods of control are available. In Hardware Control Mode, the configuration and real-time control of the device is accomplished through hardware control pins. In Software Control mode, the I²C control port is used both to configure the device and for real-time control. In Software Control Mode, several of the hardware control pins remain functional, such as the SPK_SD, SPK_FAULT, and SFT_CLIP pins. To allow the headphone amplifier / line driver to be used without needing the speaker amplifier to be active, hardware controls are provided for the headphone amplifier via the DR_MUTE and DR_UVE pins.
The power supply requirements for the TAS5760LD consist of one 3.3-V supply to power the low voltage analog and digital circuitry and one higher-voltage supply to power the output stage of the speaker amplifier. Several on-chip regulators are included on the TAS5760LD to generate the voltages necessary for the internal circuitry of the audio path. It is important to note that the voltage regulators which have been integrated are sized only to provide the current necessary to power the internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the device.
Figure 38 shows a block diagram of the speaker amplifier of the TAS5760LD. In Hardware Control mode, a limited subset of audio path controls are made available via external pins, which are pulled HIGH or LOW to configure the device. In Software Control Mode, the additional features and configurations are available. All of the available controls are discussed in this section, and the subset of controls that available in Hardware Control Mode are discussed in the respective section below.
The serial audio port (SAP) receives audio in either I²S, Left Justified, or Right Justified formats. In Hardware Control mode, the device operates only in 32, 48 or 64 x fS I²S mode. In Software Control mode, additional options for left-justified and right justified audio formats are available. The supported clock rates and ratios for Hardware Control Mode and Software Control Mode are detailed in their respective sections below.
I²S timing uses LRCK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCK is LOW for the left channel and HIGH for the right channel. A bit clock, called SCLK, runs at 32, 48, or 64 × fS and is used to clock in the data. There is a delay of one bit clock from the time the LRCK signal changes state to the first bit of data on the data lines. The data is presented in 2's-complement form (MSB-first) and is valid on the rising edge of bit clock.
Left-justified (LJ) timing also uses LRCK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCK is HIGH for the left channel and LOW for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The TAS5760LD can accept digital words from 16 to 24 bits wide and pads any unused trailing data-bit positions in the L/R frame with zeros before presenting the digital word to the audio signal path.
Right-justified (RJ) timing also uses LRCK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCK is HIGH for the left channel and LOW for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The TAS5760LD pads unused leading data-bit positions in the left/right frame with zeros before presenting the digital word to the audio signal path.
Excessive DC content in the audio signal can damage loudspeakers and even small amounts of DC offset in the signal path cause cause audible artifacts when muting and unmuting the speaker amplifier. For these reasons, the amplifier employs two separate DC blocking methods for the speaker amplifier. The first is a high-pass filter provided at the front of the data path to remove any DC from incoming audio data before it is presented to the audio path. The –3 dB corner frequencies for the filter are specified in the speaker amplifier electrical characteristics table. In Hardware Control mode, the DC blocking filter is active and cannot be disabled. In Software Control mode, the filter can be bypassed by writing a 1 to bit 7 of register 0x02. The second method is a DC detection circuit that will shutdown the power stage and issue a latching fault if DC is found to be present on the output due to some internal error of the device. This DC Error (DCE) protection is discussed in the Protection Circuitry section below.
Following the high-pass filter, a digital boost block is included to provide additional digital gain if required for a given application as well as to set an appropriate clipping point for a given GAIN[1:0] pin configuration when in Hardware Control mode. The digital boost block defaults to +6dB when the device is in Hardware Mode. In most use cases, the digital boost block will remain unchanged when operating the device in Software Control mode, as the volume control offers sufficient digital gain for most applications. The TAS5760LD's digital volume control operates from Mute to 24 dB, in steps of 0.5 dB. The equation below illustrates how to set the 8-bit volume control register at address 0x04:
Transitions between volume settings will occur at a rate of 0.5 dB every 8 LRCK cycles to ensure no audible artifacts occur during volume changes. This volume fade feature can be disabled via Bit 7 of the Volume Control Configuration Register.
A digital clipper is integrated in the oversampled domain to provide a component-free method to set the clip point of the speaker amplifier. Through the "Digital Clipper Level x" controls in the I²C control port, the point at which the oversampled digital path clips can be set directly, which in turns sets the 10% THD+N operating point of the amplifier. This is useful for applications in which a single system is designed for use in several end applications that have different power rating specifications. Its place in the oversampled domain ensures that the digital clipper is acoustically appealing and reduces or eliminates tones which would otherwise foldback into the audio band during clipping events. Figure 39 shows a block diagram of the digital clipper.
As mentioned previously, the audio signature of the amplifier when the digital clipper is active is very smooth, owing to its place in the signal chain. Figure 40 shows the typical behavior of the clipping events.
It is important to note that the actual signal developed across the speaker will be determined not only by the digital clipper, but also the analog gain of the amplifier. Depending on the analog gain settings and the PVDD level applied, clipping could occur as a result of the voltage swing that is determined by the gain being larger than the available PVDD supply rail. The gain structures are discussed in detail below for both Hardware Control Mode and Software Control Mode.
Following the digital clipper, the interpolated audio data is next sent to the Closed-Loop Class-D amplifier, whose first stage is Digital to PWM Conversion (DPC) block. In this block, the stereo audio data is translated into two pairs of complimentary pulse width modulated (PWM) signals which are used to drive the outputs of the speaker amplifer. Feedback loops around the DPC ensure constant gain across supply voltages, reduce distortion, and increase immunity to power supply injected noise and distortion. The analog gain is also applied in the Class-D amplifier section of the device. The gain structures are discussed in detail below for both Hardware Control Mode and Software Control Mode.
The switching rate of the amplifier is configurable in both Hardware Control Mode and Software Control Mode. In both cases, the PWM switching frequency is a multiple of the sample rate. This behavior is described in the respective Hardware Control Mode and Software Control Mode sections below.
The speaker amplifier in the TAS5760LD includes a robust suite of error handling and protection features. It is protected against Over-Current, Under-Voltage, Over-Voltage, Over-Temperature, DC, and Clock Errors. The status of these errors is reported via the SPK_FAULT pin and the appropriate error status register in the I²C Control Port. The error or handling behavior of the device is characterized as being either "Latching" or "Non-Latching" depending on what is required to clear the fault and resume normal operation (that is playback of audio).
For latching errors, the SPK_SD pin or the SPK_SD bit in the control port must be toggled in order to clear the error and resume normal operation. If the error is still present when the SPK_SD pin or bit transitions from LOW back to HIGH, the device will again detect the error and enter into a fault state resulting in the error status bit being set in the control port and the SPK_FAULT line being pulled LOW. If the error has been cleared (for example, the temperature of the device has decreased below the error threshold) the device will attempt to resume normal operation after the SPK_SD pin or bit is toggled and the required fault time out period (TSPK_FAULT ) has passed. If the error is still present, the device will once again enter a fault state and must be placed into and brought back out of shutdown in order to attempt to clear the error.
For non-latching errors, the device will automatically resume normal operation (that is playback) once the error has been cleared. The non-latching errors, with the exception of clock errors will not cause the SPK_FAULT line to be pulled LOW. It is not necessary to toggle the SPK_SD pin or bit in order to clear the error and resume normal operation for non-latching errors. Table 1 details the types of errors protected by the TAS5760LD's Protection Suite and how each are handled.
In both hardware and Software Control mode, the SPK_FAULT pin of the TAS5760LD serves as a fault indicator to notify the system that a fault has occurred with the speaker amplifier by being actively pulled LOW. This pin is an open-drain output pin and, unless one is provided internal to the receiver, requires an external pullup to set the net to a known value. The behavior of this pin varies based upon the type of error which has occurred.
In the case of a latching error, the fault line will remain LOW until such time that the TAS5760LD has resumed normal operation (that is the SPK_SD pin has been toggled and TSPK_FAULT has passed).
With the exception of clock errors, non-latching errors will not cause the SPK_FAULT pin to be pulled LOW. Once a non-latching error has been cleared, normal operation will resume. For clocking errors, the SPK_FAULT line will be pulled LOW, but upon clearing of the clock error normal operation will resume automatically, that is, with no TSPK_FAULT delay.
One method which can be used to convert a latching error into an auto-recovered, non-latching error is to connect the SPK_FAULT pin to the SPK_SD pin. In this way, a fault condition will automatically toggle the SPK_SD pin when the SPK_FAULT pin goes LOW and returns HIGH after the TSPK_FAULT period has passed.
ERROR | CAUSE | FAULT TYPE | ERROR IS CLEARED BY: |
---|---|---|---|
Overvoltage Error (OVE) |
PVDD level rises above that specified by OVERTHRES(PVDD) | Non-Latching (SPK_FAULT Pin is not pulled LOW) | PVDD level returning below OVETHRES(PVDD) |
Undervoltage Error (UVE) |
PVDD voltage level drops below that specified by UVEFTHRES(SPK) | Non-Latching (SPK_FAULT Pin is not pulled LOW) | PVDD level returning above UVETHRES(PVDD)
|
Clock Error (CLKE) |
One or more of the following errors has occured:
|
Non-Latching (SPK_FAULT Pin is pulled LOW) | Clocks returning to valid state |
Overcurrent Error (OCE) |
Speaker Amplifier output current has increased above the level specified by OCETHRES | Latching | TSPK_FAULT has passed AND SPK_SD Pin or Bit Toggle |
DC Detect Error (DCE) |
DC offset voltage on the speaker amplifier output has increased above the level specified by the DCETHRES | Latching | TSPK_FAULT has passed AND SPK_SD Pin or Bit Toggle |
Overtemperature Error (OTE) |
The temperature of the die has increased above the level specified by the OTETHRES | Latching | TSPK_FAULT has passed AND SPK_SD Pin or Bit Toggle AND the temperature of the device has reached a level below that which is dictated by the OTEHYST specification |
The TAS5760LD has circuitry which will protect the speakers from DC current which might occur due to an internal amplifier error. The device behavior in response to a DCE event is detailed in the table in the previous section.
A DCE event occurs when the output differential duty-cycle of either channel exceeds 60% for more than 420 msec at the same polarity. The table below shows some examples of the typical DCE Protection threshold for several values of the supply voltage. This feature protects the speaker from large DC currents or AC currents less than 2 Hz.
The minimum output offset voltages required to trigger the DC detect are listed in Table 2. The outputs must remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.
PVDD [V] | |VOS|- OUTPUT OFFSET VOLTAGE [V] |
---|---|
4.5 | 0.96 |
6 | 1.30 |
12 | 2.60 |
The TAS5760LD also integrates a versatile low-voltage analog input amplifier that can be used as a headphone amplifier or a line driver. This amplifier can operate as a ground centered 2-VRMS pop-free stereo line driver or 25-mW headphone amplifier, which allows the removal of the output dc-blocking capacitors for reduced component count and cost.
Designed using TI’s patented DirectPath™ technology, the device is capable of driving 2 VRMS into a 10-kΩ load or 23 mW into a 32-Ω headphone load, with 3.3-V supply voltage. It includes differential inputs and uses external gain-setting resistors to support a gain range of ±1 V/V to ±10 V/V. Additionally, gain can be configured individually for each channel. The outputs have ±8-kV IEC ESD protection, requiring just a simple resistor-capacitor ESD protection circuit. The device includes built-in active-mute control for pop-free audio on/off control. Additionally, an external undervoltage detector is included which will mute the output when the PVDD power supply is removed, ensuring a pop-free shutdown.
As an integrated line drive amplifier, it does not require a power supply greater than 3.3 V to generate its output signal, nor does it require a split-rail power supply. Instead, it integrates a charge pump to generate a negative supply rail that provides a clean, pop-free ground-biased analog audio output.
For systems which do not require the added flexibility of the I²C control port or do not have an I²C host controller, the TAS5760LD can be used in Hardware Control Mode. In this mode of operation, the device operates in its default configuration and any changes to the device are accomplished via the hardware control pins, described below. The audio performance between Hardware and Software Control mode is identical, however more features and functionality are available when the device is operated in Software Control mode. The behavior of these Hardware Control Mode pins is described in the sections below.
Several static I/O's are present on the TAS5760LD which are meant to be configured during PCB design and not changed during normal operation. Some examples of these are the GAIN[1:0] and PBTL/SCL pins. These pins are often referred to as being tied or pulled LOW or tied or pulled HIGH. A pin which is tied or pulled LOW has been connected directly to the system ground. The TAS5760LD is configured such that the most popular use cases for the device (that is BTL mode, 768-kHz switching frequency, and so forth) require the static I/O lines to be tied LOW. This ensures optimum thermal performance as well as BOM reduction.
Device pins that need to be tied or pulled HIGH should be connected to DVDD. For these pins, a pull-up resistor is recommended to limit the slew rate of the voltage which is presented to the pin during power up. Depending on the output impedance of the supply, and the capacitance connected to the DVDD net on the board, slew rates of this node could be high enough to trigger the integrated ESD protection circuitry at high current levels, causing damage to the device. It is not necessary to have a separate pull-up resistor for each static digital I/O pin. Instead, a single resistor can be connected to DVDD and all static I/O lines which are to be tied HIGH can be connected to that pull-up resistor. This connectivity is shown in the Typical Application Circuits. These pullup resistors are not required when the digital I/O pins are driven by a controlled driver, such as a digital control line from a systems processor, as the output buffer in the system processor will ensure a controlled slew rate.
In both Hardware and Software Control mode, the SPK_SD pin is provided to place the speaker amplifier into shutdown. Driving this pin LOW will place the device into shutdown, while pulling it HIGH (to DVDD) will bring the device out of shutdown. This is the lowest power consumption mode that the device can be placed in while the power supplies are up. If the device is placed into shutdown while in normal operation, an audible artifact may occur on the output. To avoid this, the device should first be placed into sleep mode, by pulling the SPK_SLEEP/ADR pin HIGH before pulling the SPK_SD low.
When used in Hardware Control Mode, the Serial Audio Port (SAP) accepts only I2S formatted data. Additionally, the device operates in Single-Speed Mode (SSM), which means that supported sample rates, MCLK rates, and SCLK rates are limited to those shown in the table below. Additional clocking options, including higher sample rates, are available when operating the device in Software Control Mode.
Table 3 details the supported SCLK rates for each of the available sample rate and MCLK rate configurations. For each fS and MCLK rate, the supported SCLK rates are shown and are represented in multiples of the sample rate, which is written as "x fS".
MCLK Rate
[x fS] |
||||||
---|---|---|---|---|---|---|
128 | 192 | 256 | 384 | 512 | ||
Sample Rate [kHz] | 12 | N/S | N/S | N/S | N/S | 32, 48, 64 |
16 | N/S | N/S | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
24 | N/S | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
32 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
38 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
44.1 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
48 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 |
The TAS5760LD has a soft clipper that can be used to clip the output voltage level below the supply rail. When this circuit is active, the amplifier operates as if it was powered by a lower supply voltage, and thereby enters into clipping sooner than if the circuit was not active. The result is clipping behavior very similar to that of clipping at the PVDD rail, in contrast to the digital clipper behavior which occurs in the oversampled domain of the digital path. The point at which clipping begins is controlled by a resistor divider from GVDD_REG to ground, which sets the voltage at the SFT_CLIP pin. The precision of the threshold at which clipping occurs is dependent upon the voltage level at the SFT_CLIP pin. Because of this, increasing the precision of the resistors used to create the voltage divider, or using an external reference will increase the precision of the point at which the device enters into clipping. To ensure stability, and soften the edges of the clipping event, a capacitor should be connected from pin SFT_CLIP to ground.
To move the output stage into clipping, the soft clipper circuit limits the duty cycle of the output PWM pulses to a fixed maximum value. After filtering this limit applied to the duty cycle resembles a clipping event at a voltage below that of the PVDD level. The peak voltage level attainable when the soft clipper circuit is active, called VP in the example below, is approximately 4 times the voltage at the SFT_CLIP pin, noted as VSFT_CLIP. This voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance, as shown in the equation below.
Where:
RS is the total series resistance including RDS(on), and output filter resistance.
RL is the load resistance.
VP is the peak amplitude achievable when the soft clipper circuit is active (As mentioned previously, VP = [4 x VSFT_CLIP], provided that [4 x VSFT_CLIP] < PVDD.)
POUT (10%THD) ≈ 1.25 × POUT (unclipped)
If the PVDD level is below (4 x VSFT_CLIP) clipping will occur due to clipping at PVDD before the clipping due to the soft clipper circuit becomes active.
PVDD [V] | SFT_CLIP Pin Voltage [V] | Resistor to GND [kΩ] | Resistor to GVDD [kΩ] | Output Voltage [Vrms] |
---|---|---|---|---|
12 | GVDD | (Open) | 0 | 10.33 |
12 | 2.25 | 24 | 51 | 9.00 |
12 | 1.5 | 18 | 68 | 6.30 |
In Hardware Control mode, the PWM switching frequency of the TAS5760LD is configurable via the FREQ/SDA pin. When connected to the system ground, the pin sets the output switching frequency to 16 × fS. When connected to DVDD through a pull-up resistor, as shown in the Typical Application Circuits, the pin sets the output switching frequency to 8 × fS. More switching frequencies are available when the TAS5760LD is used in Software Control Mode.
The TAS5760LD can be configured to drive a single speaker with the two output channels connected in parallel. This mode of operation is called Parallel Bridge Tied Load (PBTL) mode. This mode of operation effectively reduces the output impedance of the amplifier in half, which in turn reduces the power dissipated in the device due to conduction losses through the output FETs. Additionally, since the output channels are working in parallel, it also doubles the amount of current the speaker amplifier can source before hitting the over-current error threshold.
The device can be placed operated in PBTL mode in either Hardware Control Mode or in Software Control Mode, via the I²C Control Port. For instructions on placing the device in PBTL via the I²C Control Port, see Software Control Mode.
To place the TAS5760LD into PBTL Mode when operating in Hardware Control Mode, the PBTL/SCL pin should be pulled HIGH (that is, connected to the DVDD supply through a pull-up resistor). If the device is to operate in BTL mode instead, the PBTL/SCL pin should be pulled LOW, that is connected to the system supply ground. When operated in PBTL mode, the output pins should be connected as shown in the Typical Application Circuit Diagrams.
In PBTL mode, the amplifier selects its source signal from the right channel of the stereo signal presented on the SDIN line of the Serial Audio Port. To select the right channel of the stereo signal, the LRCK can be inverted in the processor that is sending the serial audio data to the TAS5760LD.
In Hardware Control mode, pulling the SPK_SLEEP/ADR pin HIGH gracefully transitions the switching of the output devices to a non-switching state or "High-Z" state. This mode of operation is similar to mute in that no audio is present on the outputs of the device. However, unlike the 50/50 mute available in the I²C Control Port, sleep mode saves quiescent power dissipation by stopping the speaker amplifier output transitors from switching. This mode of operation saves quiescent current operation but keeps signal path blocks active so that normal operation can resume more quickly than if the device were placed into shutdown. It is recommended to place the device into sleep mode before stopping the audio signal coming in on the SDIN line or before bringing down the power supplies connected to the TAS5760LD in order to avoid audible artifacts.
In Hardware Control Mode, a combination of digital gain and analog gain is used to provide the overall gain of the speaker amplifier. The decode of the two pins "SPK_GAIN1" and "SPK_GAIN0" sets the gain of the speaker amplifier. Additionally, pulling both of the SPK_SPK_GAIN[1:0] pins HIGH places the device into software control mode.
As seen in Figure 42, the audio path of the TAS5760LD consists of a digital audio input port, a digital audio path, a digital to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds the output information back into the DPC block to correct for distortion sensed on the output pins. The total amplifier gain is comprised of digital gain, shown as GDIG in the digital audio path and the analog gain from the input of the analog modulator GANA to the output of the speaker amplifier power stage.
As shown in Figure 42, the first gain stage for the speaker amplifier is present in the digital audio path. It consists of the volume control and the digital boost block. The volume control is set to 0dB by default and, in Hardware Control mode, it does not change. For all settings of the SPK_GAIN[1:0] pins, the digital boost block remains at +6 dB as analog gain block is transitioned through 19.2, 22.6, and 25 dBV.
The gain configurations provided in Hardware Control mode were chosen to align with popular power supply levels found in many consumer electronics and to balance the trade-off between maximum power output before clipping and noise performance. These gain settings ensure that the output signal can be driven into clipping at those popular PVDD levels. If the power level required is lower than that which is possible with the PVDD level, a lower gain setting can be used. Additionally, if clipping at a level lower than the PVDD supply is desired, the digital clipper or soft clipper can be used.
The values of GDIG and GANA for each of the SPK_GAIN[1:0] settings are shown in the table below. Additionally, the recommended PVDD level for each gain setting, along with the typical unclipped peak to peak output voltage swing for a 0dBFS input signal is provided. The peak voltage levels in the table below should only be used to understand the peak target output voltage swing of the amplifier if it had not been limited by clipping at the PVDD rail.
PVDD Level | Recommended SPK_GAIN[1:0] Pins Setting |
Digital Boost [dB] |
A_GAIN [dBV] |
VPk Acheivable Voltage Swing (If output is not clipped at PVDD) |
---|---|---|---|---|
12 | 00 | 6 | 19.2 | 12.90 |
15 | 01 | 6 | 22.6 | 19.08 |
This setting is not recommended for voltages supported by the TAS5760LD | 10 | 6 | 25 | This setting is not recommended for voltages supported by the TAS5760LD |
- | 11 | (Gain is controlled via I²C Port) |
Configuration of the gain of the amplifier is important to the overall noise and output power performance of the TAS5760LD. Higher gain settings mean that more power can be driven from an amplifier before it becomes voltage limited. Moreover, when output clipping "at the rail" is desired, it becomes important that there be enough voltage gain in the signal path to drive the output signal above the PVDD level in order to "clip" the output signal at the PVDD level in the output stage. Another desirable aspect of higher gain settings is that the dynamic headroom of an amplifier is increased with higher gain settings, which increases the overall dynamic audio quality of the signal being amplified.
With these advantages in mind, it may seem that setting the gain at the highest setting available would be appropriate. However, there are some drawbacks to having a gain that is set arbitrarily high. The first drawback is that a higher gain setting results in increased amplification of any noise that is present in the signal path. If the gain is set too high, and the speaker is sensitive enough, this may result in an audible "hiss" at the speakers when no audio is playing. Another consideration is that the speakers used in the system may not be rated for operation at the power levels which would be possible for the given PVDD supply that is present in the system. For this reason, it may be necessary to limit the voltage swing of the amplifier via a lower gain setting to reduce the voltage presented, and therefore, the power delivered, to the speaker.
NOTE
A higher gain setting can be used, provided the noise performance is acceptable and the power delivered to the speaker remains within the safe operating area (SOA) of the speaker, using the soft clipper if necessary to set the clip point within the SOA of the speaker.
The TAS5760LD can be used in Hardware Control Mode or Software Control Mode. In order to place the device in software control mode, the two gain pins (GAIN[1:0]) should be pulled HIGH. When this is done, the PBTL/SCL and FREQ/SDA pins are allocated to serve as the clock and data lines for the I²C Control Port.
In both hardware and Software Control mode, the SPK_SD pin is provided to place the speaker amplifier into shutdown. Driving this pin LOW will place the device into shutdown, while driving it HIGH (DVDD) will bring the device out of shutdown. This is the lowest power consumption mode that the device can be placed in while the power supplies are up. If the device is placed into shutdown while in normal operation, an audible artifact may occur on the output. To avoid this, the device should first be placed into sleep mode, by pulling the SPK_SLEEP/ADR pin HIGH before pulling the SPK_SD low.
In Software Control mode, additional digital audio data formats and clock rates are made available via the I²C control port. With these controls, the audio format can be set to left justified, right justified, or I²S formatted data.
When used in Software Control mode, the device can be placed into double speed mode to support higher sample rates, such as 88.2 kHz and 96 kHz. The tables below detail the supported SCLK rates for each of the available sample rate and MCLK rate configurations. For each fS and MCLK Rate the support SCLK rates are shown and are represented in multiples of the sample rate, which is written as "x fS".
MCLK Rate [x fS] | ||||||
---|---|---|---|---|---|---|
128 | 192 | 256 | 384 | 512 | ||
Sample Rate [kHz] | 12 | N/S | N/S | N/S | N/S | 32, 48, 64 |
16 | N/S | N/S | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
24 | N/S | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
32 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
38 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
44.1 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | |
48 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 |
MCLK Rate [x fS] | |||||
---|---|---|---|---|---|
64 | 128 | 192 | 256 | ||
Sample Rate [kHz] | 88.2 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 |
96 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 | 32, 48, 64 |
The TAS5760LD can be configured to drive a single speaker with the two output channels connected in parallel. This mode of operation is called Parallel Bridge Tied Load (PBTL) mode. This mode of operation effectively reduces the on resistance of the amplifier in half, which in turn reduces the power dissipated in the device due to conduction losses through the output FETs. Additionally, since the output channels are working in parallel, it also doubles the amount of current the speaker amplifier can source before hitting the over-current error threshold.
It should be noted that the device can be placed operated in PBTL mode in either Hardware Control Mode or in Software Control Mode, via the I²C Control Port. For instructions on placing the device in PBTL via the PBTL/SCL Pin, see Hardware Control Mode.
To place the TAS5760LD into PBTL Mode when operating in Software Control Mode, the Bit 7 of the Analog Control Register (0x06) should be set in the control port. This bit is cleared by default to configure the device for BTL mode operation. An additional control available in software mode control is PBTL Channel Select, which selects which of the two channels presented on the SDIN line will be used for the input signal for the amplifier. This is found at Bit 1 of the Analog Control Register (0x06). When operated in PBTL mode, the output pins should be connected as shown in the Typical Application Circuit Diagrams.
As shown in Figure 43, the audio path of the TAS5760LD consists of a digital audio input port, a digital audio path, a digital to analog converter, an analog modulator, a gate driver stage, a Class D power stage, and a feedback loop which feeds the output information back into the analog modulator to correct for distortion sensed on the output pins. The total amplifier gain is comprised of digital gain, shown as GDIG in the digital audio path and the analog gain from the input of the analog modulator GANA to the output of the speaker amplifier power stage.
The analog and digital gain are configured directly when operating in Software Control mode. It is important to note that the digital boost block is separate from the volume control. The digital boost block should be set before the speaker amplifier is brought out of mute and not changed during normal operation. In most cases, the digital boost can be left in its default configuration, and no further adjustment is necessary. As mentioned previously, the analog gain is directly set via the I²C control port in software control mode.
Configuration of the gain of the amplifier is important to the overall noise and output power performance of the TAS5760LD. Higher gain settings mean that more power can be driven from an amplifier before it becomes voltage limited. Moreover, when output clipping "at the rail" is desired, it becomes important that there be enough voltage gain in the signal path to drive the output signal above the PVDD level in order to "clip" the output signal at the PVDD level in the output stage. Another desirable aspect of higher gain settings is that the dynamic headroom of an amplifier is increased with higher gain settings, which increases the overall dynamic audio quality of the signal being amplified.
With these advantages in mind, it may seem that setting the gain at the highest setting available would be appropriate. However, there are some drawbacks to having a gain that is set arbitrarily high. The first drawback is that a higher gain setting results in increased amplification of any noise that is present in the signal path. If the gain is set too high, and the speaker is sensitive enough, this may result in an audible "hiss" at the speakers when no audio is playing. Another consideration is that the speakers used in the system may not be rated for operation at the power levels which would be possible for the given PVDD supply that is present in the system. For this reason it may be necessary to limit the voltage swing of the amplifier via a lower gain setting to reduce the voltage presented, and therefore the power delivered, to the speaker.
NOTE
A higher gain setting can be used, provided the noise performance is acceptable and the power delivered to the speaker remains within the safe operating area (SOA) of the speaker, using the soft clipper if necessary to set the clip point within the SOA of the speaker.
The TAS5760LD includes an I²C control port for increased flexibility and extended feature set.
Each device on the I²C bus has a unique address that allows it to appropriately transmit and receive data to and from the I²C master controller. As part of the I²C protocol, the I²C master broadcast an 8-bit word on the bus that contains a 7-bit device address in the upper 7 bits and a read or write bit for the LSB. The TAS5760LD has a configurable I²C address. The SPK_SLEEP/ADR can be used to set the device address of the TAS5760LD. In Software Control mode, the seven bit I²C device address is configured as “110110x[R/W]”, where “x” corresponds to the state of the SPK_SLEEP/ADR pin at first power up sequence of the device. Upon application of the power supplies, the device latches in the value of the SPK_SLEEP/ADR pin for use in determining the I²C address of the device. If the SPK_SLEEP/ADR pin is tied LOW at power up (that is connected to the system ground), the device address will be set to 1101100[R/W]. If it is pulled HIGH (that is connected to the DVDD supply), the address will be set to 1101101[R/W] at power up.
The TAS5760LD device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a START condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is HIGH to indicate START and STOP conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 44. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5760LD holds SDA LOW during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus.
There is no limit on the number of bytes that can be transmitted between START and STOP conditions. When the last word transfers, the master generates a STOP condition to release the bus. A generic data transfer sequence is shown in Figure 44.
As shown in Figure 45, a single-byte data-write transfer begins with the master device transmitting a START condition followed by the I²C and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C and the read/write bit, the TAS5760LD responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the TAS5760LD register being accessed. After receiving the address byte, the TAS5760LD again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5760LD again responds with an acknowledge bit. Finally, the master device transmits a STOP condition to complete the single-byte data-write transfer.
As shown in Figure 46, a data-read transfer begins with the master device transmitting a START condition, followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5760LD address and the read/write bit, TAS5760LD responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another START condition followed by the TAS5760LD address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5760LD again responds with an acknowledge bit. Next, the TAS5760LD transmits the data byte from the register being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a STOP condition to complete the data-read transfer.
Adr. (Dec) |
Adr. (Hex) |
Register Name | Default (Binary) | Default (Hex) |
|||||||
---|---|---|---|---|---|---|---|---|---|---|---|
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ||||
0 | 0 | Device Identification | Device Identification | 0x00 | |||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||
1 | 1 | Power Control | DigClipLev[19:14] | SPK_SLEEP | SPK_SD | 0xFD | |||||
1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | ||||
2 | 2 | Digital Control | HPF Bypass | Reserved | Digital Boost | SS/DS | Serial Audio Input Format | 0x14 | |||
0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | ||||
3 | 3 | Volume Control Configuration | Fade | Reserved | Reserved | Reserved | Reserved | Reserved | Mute R | Mute L | 0x80 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||
4 | 4 | Left Channel Volume Control | Volume Left | 0xCF | |||||||
1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | ||||
5 | 5 | Right Channel Volume Control | Volume Right | 0xCF | |||||||
1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | ||||
6 | 6 | Analog Control | PBTL Enable | PWM Rate Select | A_GAIN | PBTL Ch Sel | Reserved | 0x51 | |||
0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | ||||
7 | 7 | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | 0x00 | |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||
8 | 8 | Fault Configuration and Error Status | Reserved | OCE Thres | CLKE | OCE | DCE | OTE | 0x00 | ||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||
9 | 9 | Reserved | - | - | - | - | - | - | - | - | - |
... | Reserved | - | - | - | - | - | - | - | - | - | |
15 | F | Reserved | - | - | - | - | - | - | - | - | - |
16 | 10 | Digital Clipper 2 | DigClipLev[13:6] | 0xFF | |||||||
1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | ||||
17 | 11 | Digital Clipper 1 | DigClipLev[5:0] | 0xFC | |||||||
1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Device Identification | |||||||
R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | Device Identification | R | 0 | Device Identification - TAS5760Lxx |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DigClipLev[19:14] | SPK_SLEEP | SPK_SD | |||||
R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | DigClipLev[19:14] | R/W | 1 | The digital clipper is decoded from 3 registers- DigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0]. DigClipLev[19:14], shown here, represents the upper 6 bits of the total of 20 bits that are used to set the Digital Clipping Threshold. |
1 | SPK_SLEEP | R/W | 0 | Sleep Mode 0: Device is not in sleep mode. 1: Device is placed in sleep mode (In this mode, the power stage is disabled to reduce quiescent power consumption over a 50/50 duty cycle mute, while low-voltage blocks remain on standby. This reduces the time required to resume playback when compared with entering and exiting full shut down.). |
0 | SPK_SD | R/W | 1 | Speaker Shutdown 0: Speaker amplifier is shut down (This is the lowest power mode available when the device is connected to power supplies. In this mode, circuitry in both the DVDD and PVDD domain are powered down to minimize power consumption.). 1: Speaker amplifier is not shut down. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HPF Bypass | Reserved | Digital Boost | SS/DS | Serial Audio Input Format | |||
R/W | R | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Fade | Reserved | Mute R | Mute L | ||||
R/W | R | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Fade | R/W | 1 | Volume Fade Enable 0: Volume fading is disabled. 1: Volume fading is enabled. |
6:2 | Reserved | R | 0 | This control is reserved and must not be changed from its default setting. |
1 | Mute R | R/W | 0 | Mute Right Channel 0: The right channel is not muted 1: The right channel is muted (In software mute, most analog and digital blocks remain active and the speaker amplifier outputs transition to a 50/50 duty cycle.) |
0 | Mute L | R/W | 0 | Mute Left Channel 0: The left channel is not muted 1: The left channel is muted (In software mute, most analog and digital blocks remain active and the speaker amplifier outputs transition to a 50/50 duty cycle.) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Volume Left | |||||||
R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | Volume Left | R/W | 11001111 | Left Channel Volume Control 11111111: Channel Volume is +24 dB 11111110: Channel Volume is +23.5 dB 11111101: Channel Volume is +23.0 dB ...11001111: Channel Volume is 0 dB (Default) ...00000111: Channel Volume is -100 dB Any setting less than 00000111 places the channel in Mute |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Volume Right | |||||||
R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | Volume Right | R/W | 11001111 | Right Channel Volume Control 11111111: Channel Volume is +24 dB 11111110: Channel Volume is +23.5 dB 11111101: Channel Volume is +23.0 dB ...11001111: Channel Volume is 0 dB (Default) ...00000111: Channel Volume is -100 dB Any setting less than 00000111 places the channel in Mute |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PBTL Enable | PWM Rate Select | A_GAIN | PBTL Ch Sel | Reserved | |||
R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PBTL Enable | R/W | 0 | PBTL Enable 0: Device is placed in BTL mode. 1: Device is placed in PBTL mode. |
6:4 | PWM Rate Select | R/W | 101 | PWM Rate Select 000: Output switching rate of the Speaker Amplifier is 6 * LRCK. 001: Output switching rate of the Speaker Amplifier is 8 * LRCK. 010: Output switching rate of the Speaker Amplifier is 10 * LRCK. 011: Output switching rate of the Speaker Amplifier is 12 * LRCK. 100: Output switching rate of the Speaker Amplifier is 14 * LRCK. 101: Output switching rate of the Speaker Amplifier is 16 * LRCK. (Default) 110: Output switching rate of the Speaker Amplifier is 20 * LRCK. 111: Output switching rate of the Speaker Amplifier is 24 * LRCK. Note that all rates listed above are valid for single speed mode. For double speed mode, switching frequency is half of that represented above. |
3:2 | A_GAIN | R/W | 00 |
00: Analog Gain Setting is 19.2 dBV.(Default) 01: Analog Gain Setting is 22.6 dBV. 10: Analog Gain Setting is 25 dBV. 11: This setting is reserved and must not be used. |
1 | PBTL Ch Sel | R/W | 0 | Channel Selection for PBTL Mode 0: When placed in PBTL mode, the audio information from the Right channel of the serial audio input stream is used by the speaker amplifier. 1: When placed in PBTL mode, the audio information from the Left channel of the serial audio input stream is used by the speaker amplifier. |
0 | Reserved | R/W | 1 | This control is reserved and must not be changed from its default setting. |
The controls in this section of the control port are reserved and must not be used.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | OCE Thres | CLKE | OCE | DCE | OTE | ||
R | R/W | R | R | R | R |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | Reserved | R | 0 | This control is reserved and must not be changed from its default setting. |
5:4 | OCE Thres | R/W | 00 | OCE Threshold 00: Threshold is set to the default level specified in the electrical characteristics table. (Default) 01: Threshold is reduced to 75% of the evel specified in the electrical characteristics table. 10: Threshold is reduced to 50% of the evel specified in the electrical characteristics table. 11: Threshold is reduced to 25% of the evel specified in the electrical characteristics table. |
3 | CLKE | R | 0 | Clock Error Status 0: Clocks are valid and no error is currently detected. 1: A clock error is occuring (This error is non-latching, so intermittent clock errors will be cleared when clocks re-enter valid state and the device will resume normal operation automatically. This bit will likewise be cleared once normal operation resumes.). |
2 | OCE | R | 0 | Over Current Error Status 0: The output current levels of the speaker amplifier outputs are below the OCE threshold. 1: The DC offset level of the outputs has exceeded the OCE threshold, causing an error (This is a latching error and SPK_SD must be toggled after an OCE event for the device to resume normal operation. This bit will remain HIGH until SPK_SD is toggled.). |
1 | DCE | R | 0 | Output DC Error Status 0: The DC offset level of the speaker amplifier outputs are below the DCE threshold. 1: The DC offset level of the speaker amplifier outputs has exceeded the DCE threshold, causing an error (This is a latching error and SPK_SD must be toggled after an DCE event for the device to resume normal operation. This bit will remain HIGH until SPK_SD is toggled.). |
0 | OTE | R | 0 | Over-Temperature Error Status 0: The temperature of the die is below the OTE threshold. 1: The temperature of the die has exceeded the level specified in the electrical characteristics table. (This is a latching error and SPK_SD must be toggled for the device to resume normal operation. This bit will remain HIGH until SPK_SD is toggled.). |
The controls in this section of the control port are reserved and must not be used.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DigClipLev[13:6] | |||||||
R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | DigClipLev[13:6] | R/W | 1 | The digital clipper is decoded from 3 registers- DigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0]. DigClipLev[13:6], shown here, represents the [13:6] bits of the total of 20 bits that are used to set the Digital Clipping Threshold. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DigClipLev[5:0] | Reserved | ||||||
R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | DigClipLev[5:0] | R/W | 1 | The digital clipper is decoded from 3 registers- DigClipLev[19:14], DigClipLev[13:6], and DigClipLev[5:0]. DigClipLev[5:0], shown here, represents the [5:0] bits of the total of 20 bits that are used to set the Digital Clipping Threshold. |
1:0 | Reserved | R/W | 0 | These controls are reserved and should not be changed from there default values. |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
These typical connection diagrams highlight the required external components and system level connections for proper operation of the device in several popular use cases.
Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in all available modes of operation. Additionally, some of the application circuits are available as reference designs and can be found on the TI website. Also see the TAS5760LD's product page for information on ordering the EVM. Not all configurations are available as reference designs; however, any design variation can be supported by TI through schematic and layout reviews. Visit support.ti.com for additional design assistance. Also, join the audio amplifier discussion forum at http://e2e.ti.com.
These application circuits detail the recommended component selection and board configurations for the TAS5760LD device. Note that in Software Control mode, the clipping point of the amplifier and thus the rated power of the end equipment can be set using the digital clipper if desired. Additionally, if the sonic signature of the soft clipper is preferred, it can be used in addition to or in lieu of the digital clipper. The software control application circuit detailed in this section shows the soft clipper in its bypassed state, which results in a lower BOM count than when using the soft clipper. The trade-off between the sonic characteristics of the clipping events in the amplifier and BOM minimization can be chosen based upon the design goals related to the end product.
For this design example, use the parameters listed in Table 19 as the input parameters.
PARAMETER | EXAMPLE |
---|---|
Low Power Supply | 3.3 V |
High Power Supply | 5 V to 15 V |
Host Processor | I2S Compliant Master |
I2C Compliant Master | |
GPIO Control | |
Output Filters | Inductor-Capacitor Low Pass Filter |
Speakers | 4 Ω to 8 Ω |
NOTE
Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.
NOTE
Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.
Figure 57 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.
It is important to note that when the device is operated in Software Control Mode, the customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.
The digital I/O lines of the TAS5760LD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.
The start up and shutdown procedures for both Hardware Control Mode and Software Control Mode are shown below.
Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 58 illustrates the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often large in value. The line load (typical resistive values of 600 Ω to 10 kΩ) combines with the dc blocking capacitors to form a high-pass filter. Equation 3 shows the relationship between the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC).
CO can be determined using Equation 4, where the load impedance and the cutoff frequency are known.
If fC is low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal.
The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split-supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram and waveform of Figure 58 illustrate the ground-referenced line-driver architecture. This is the architecture of the headphone / line driver inside of the TAS5760LD.
The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge-pump capacitor in order to allow maximum charge transfer. Low-ESR capacitors are an ideal selection, and a value of 1 µF is typical. Capacitor values that are smaller than 1 µF can be used, but the maximum output voltage may be reduced and the device may not operate to specifications. If the TAS5760LD is used in highly noise-sensitive circuits, it is recommended to add a small LC filter on the DRVDD connection.
The TAS5760LD contains a DirectPath line-driver amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good, low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 µF, placed as close as possible to the device DRVDD lead works best. Placing this decoupling capacitor close to the TAS5760LD is important for the performance of the amplifier. For filtering lower-frequency noise signals, a 10-µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device.
The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the headphone amplifier / line driver inside the TAS5760LD are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.
Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too high increases the noise of the amplifier. Table 20 lists the recommended resistor values for different inverting-input gain settings.
GAIN | INPUT RESISTOR VALUE, RIN | FEEDBACK RESISTOR VALUE, Rfb |
---|---|---|
–1 V/V | 10 kΩ | 10 kΩ |
–1.5 V/V | 8.2 kΩ | 12 kΩ |
–2 V/V | 15 kΩ | 30 kΩ |
–10 V/V | 4.7 kΩ | 47 kΩ |
Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible with the headphone amplifier / line driver inside the TAS5760LD, as it can be used like a standard operational amplifier. Several filter topologies can be implemented, both single-ended and differential. In Figure 59, multi-feedback (MFB) with differential input and single-ended input are shown.
An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum.
The component values can be calculated with the help of the TI FilterPro™ program available on the TI Web site at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html.
The resistor values should have a low value for obtaining low noise, but should also have a high enough value to get a small-size ac-coupling capacitor. With the proposed values of R1 = 15 kΩ, R2 = 30 kΩ, and R3 = 43 kΩ, a dynamic range (DYR) of 106 dB can be achieved with a 1-mF input ac-coupling capacitor.
External undervoltage detection can be used to mute/shut down the heaphone / line driver amplifier in the TAS5760LD before an input device can generate a pop. The shutdown threshold at the UVP pin is 1.25 V. The user selects a resistor divider to obtain the shutdown threshold and hysteresis for the specific application. The thresholds can be determined as follows:
For example, to obtain VUVP = 3.8 V and 1-V hysteresis, we can use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ.
DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the headphone amplifier / line driver inside the TAS5760LD. These capacitors block the dc portion of the audio source and allow the headphone / line driver amplifier inside the TAS5760LD.
These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using Equation 7. For this calculation, the capacitance used is the input-blocking capacitor, and the resistance is the input resistor chosen from Table 20; then the frequency and/or capacitance can be determined when one of the two values is given.
It is recommended to use electrolytic capacitors or high-voltage-rated capacitors as input blocking capacitors to ensure minimal variation in capacitance with input voltages. Such variation in capacitance with input voltages is commonly seen in ceramic capacitors and can increase low-frequency audio distortion.
The gain-setting resistors, RIN and Rfb, must be placed close to their respective pins to minimize capacitive loading on these input pins and to ensure maximum stability of the headphone / line driver inside the TAS5760LD. For the recommended PCB layout, see the TAS5760LD EVM User's Guide, SLOU371.
PLOT TITLE | PLOT NUMBER |
---|---|
Figure 1. Output Power vs PVDD | G001 |
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W | G024 |
Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven | G027 |
Figure 7. Efficiency vs Output Power | G030 |
Figure 8. Crosstalk vs Frequency | G031 |
Figure 9. PVDD PSRR vs Frequency | G019 |
Figure 10. DVDD PSRR vs Frequency | G020 |
Figure 11. Idle Current Draw vs PVDD (Filterless) | G042 |
Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) | G023 |
Figure 13. Shutdown Current Draw vs PVDD (Filterless) | G022 |
Figure 14. Output Power vs PVDD | G039 |
Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W | G002 |
Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven | G008 |
Figure 20. Efficiency vs Output Power | G014 |
Figure 21. Crosstalk vs Frequency | G018 |
Figure 22. PVDD PSRR vs Frequency | G019 |
Figure 23. Idle Current Draw vs PVDD (Filterless) | G045 |
Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) | G044 |
Figure 25. Shutdown Current Draw vs PVDD (Filterless) | G022 |
For this design example, use the parameters listed in Table 22 as the input parameters.
PARAMETER | EXAMPLE |
---|---|
Low Power Supply | 3.3 V |
High Power Supply | 5 V to 15 V |
Host Processor | I2S Compliant Master |
GPIO Control | |
Output Filters | Inductor-Capacitor Low Pass Filter |
Speakers | 4 Ω to 8 Ω |
The digital I/O lines of the TAS5760LD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.
PLOT TITLE | PLOT NUMBER |
---|---|
Figure 1. Output Power vs PVDD | G001 |
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W | G024 |
Figure 4. Idle Channel Noise vs PVDD | G026 |
Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven | G027 |
Figure 7. Efficiency vs Output Power | G030 |
Figure 8. Crosstalk vs Frequency | G031 |
Figure 9. PVDD PSRR vs Frequency | G019 |
Figure 10. DVDD PSRR vs Frequency | G020 |
Figure 11. Idle Current Draw vs PVDD (Filterless) | G042 |
Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) | G023 |
Figure 13. Shutdown Current Draw vs PVDD (Filterless) | G022 |
Figure 14. Output Power vs PVDD | G039 |
Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W | G002 |
Figure 17. Idle Channel Noise vs PVDD | G006 |
Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven | G008 |
Figure 20. Efficiency vs Output Power | G014 |
Figure 21. Crosstalk vs Frequency | G018 |
Figure 22. PVDD PSRR vs Frequency | G019 |
Figure 23. Idle Current Draw vs PVDD (Filterless) | G045 |
Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) | G044 |
Figure 25. Shutdown Current Draw vs PVDD (Filterless) | G022 |
For this design example, use the parameters listed in Table 24 as the input parameters.
PARAMETER | EXAMPLE |
---|---|
Low Power Supply | 3.3 V |
High Power Supply | 5 V to 15 V |
Host Processor | I2S Compliant Master |
I2C Compliant Master | |
GPIO Control | |
Output Filters | Inductor-Capacitor Low Pass Filter |
Speakers | 4 Ω to 8 Ω |
NOTE
Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.
NOTE
Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.
Figure 62 above details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.
It is important to note that when the device is operated in Software Control Mode, the customary pull-up resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, since they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.
The digital I/O lines of the TAS5760LD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.
PLOT TITLE | PLOT NUMBER |
---|---|
Figure 27. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W | G032 |
Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input | G035 |
Figure 37. Efficiency vs Output Power | G038 |
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W | G004 |
Figure 35. THD+N vs Output Power With PVDD = 12 V | G011 |
Figure 7. Efficiency vs Output Power | G015 |
For this design example, use the parameters listed in Table 26 as the input parameters.
PARAMETER | EXAMPLE |
---|---|
Low Power Supply | 3.3 V |
High Power Supply | 5 V to 15 V |
Host Processor | I2S Compliant Master |
GPIO Control | |
Output Filters | Inductor-Capacitor Low Pass Filter |
Speakers | 4 Ω to 8 Ω |
Figure 63 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.
The digital I/O lines of the TAS5760LD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.
PLOT TITLE | PLOT NUMBER |
---|---|
Figure 32. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W | G032 |
Figure 34. Idle Channel Noise vs PVDD | G034 |
Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input | G035 |
Figure 37. Efficiency vs Output Power | G038 |
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W | G004 |
Figure 17. Idle Channel Noise vs PVDD | G007 |
Figure 35. THD+N vs Output Power With PVDD = 12 V | G011 |
Figure 7. Efficiency vs Output Power | G015 |