TAS5760LD General-Purpose I2S Input Class-D Amplifier With DirectPath™ Headphone and Line Driver
- SLOS781C July 2013 – November 2017 TAS5760LD
  
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DATA SHEET

TAS5760LD General-Purpose I2S Input Class-D Amplifier With DirectPath™ Headphone and Line Driver

1 Features

Audio I/O Configuration:
- Single Stereo I²S Input
- Stereo Bridge Tied Load (BTL) or Mono Parallel Bridge Tied Load (PBTL) Operation
- 32, 44.1, 48, 88.2, 96 kHz Sample Rates
- Headphone Amplifier / Line Driver
General Operational Features:
- Selectable Hardware or Software Control
- Integrated Digital Output Clipper
- Programmable I²C Address (1101100[^R/_W] or 1101101[^R/_W])
- Closed-Loop Amplifier Architecture
- Adjustable Switching Frequency for Speaker Amplifier
Robustness Features:
- Clock Error, DC, and Short-Circuit Protection
- Overtemperature and Programmable Overcurrent Protection
Audio Performance (PVDD = 12 V, R_SPK = 8 Ω, SPK_GAIN[1:0] Pins = 01)
- Idle Channel Noise = 65 µVrms (A-Wtd)
- THD+N = 0.09% (at 1 W, 1 kHz)
- SNR = 100 dB A-Wtd (Ref. to THD+N = 1%)

2 Applications

LCD/LED TV and Multipurpose Monitors
Sound Bars, Docking Stations, PC Audio
General-Purpose Audio Equipment

3 Description

The TAS5760LD is a stereo I2S input device which includes hardware and software (I²C) control modes, integrated digital clipper, several gain options, and a wide power supply operating range to enable use in a multitude of applications. The TAS5760LD operates with a nominal supply voltage from 4.5 to 15 VDC. The device has an integrated DirectPath™ headphone amplifier and line driver to increase system level integration and reduce total solution costs.

An optimal mix of thermal performance and device cost is provided in the 120-mΩ R_DS(ON) of the output MOSFETs. Additionally, a thermally enhanced 48-Pin TSSOP provides excellent operation in the elevated ambient temperatures found in modern consumer electronic devices.

The entire TAS5760xx family is pin-to-pin compatible in the 48-Pin TSSOP package. Alternatively, to achieve the smallest possible solutions size for applications where pin-to-pin compatibility and a headphone or line driver are not required, a 32-Pin TSSOP package is offered for the TAS5760M and TAS5760L devices. The I²C register map in all of the TAS5760xx devices are identical, to ensure low development overhead when choosing between devices based upon system-level requirements.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TAS5760LD	HTSSOP (48)	12.50 mm × 6.10 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Functional Block Diagram

Output Power vs PVDD

TAS5760LD G001_BTL_384_POvsVDD_SLOS781.png

NOTE:

Thermal Limits were determined via the TAS5760xxEVM

4 Revision History

Changes from B Revision (May 2017) to C Revision

Deleted the 64 MCLK Rate column in Table 3 Go
Deleted the 64 MCLK Rate column in Table 6 Go

Changes from A Revision (July 2015) to B Revision

Changed Features list item, Audio Performance From: R_LOAD = 8Ω To: R_SPK = 8ΩGo
Changed From: Voltage at speaker amplifier output pins To: Speaker Amplifier Output Voltage in the Abs Max tableGo
Changed the Soft Clipper Control (SFT_CLIP Pin) sectionGo
Updated the Register Map section to the new format. No new data addedGo
Deleted statement of 64-kHz sample rate Go
Changed Figure 58 device number reference From: TAS5760MD to TAS5760xDGo
Changed paragraph text following Figure 58 From: This is the architecture of the TAS5760LD. To: This is the architecture of the headphone / line driver inside of the TAS5760LD.Go

Changes from * Revision (July 2013) to A Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
Modified Master clock and Serial Audio Port specifications to reflect the clocking improvements of the device. Go

5 Pin Configuration and Functions

DCA Package

48 Pins TSSOP

Top View

Pin Functions

PIN		TYPE	INTERNAL TERMINATION	DESCRIPTION
NAME	NO.	TYPE	INTERNAL TERMINATION	DESCRIPTION
AVDD	46	P	-	Power supply for internal analog circuitry
ANA_REF	4	P	-	Connection point for internal reference used by ANA_REG and VCOM filter capacitors.
ANA_REG	2	P	-	Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
BSTRPA-	39	P	-	Connection point for the SPK_OUTA- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA-
BSTRPA+	43	P	-	Connection point for the SPK_OUTA+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTA+
BSTRPB-	38	P	-	Connection point for the SPK_OUTB- bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB-
BSTRPB+	34	P	-	Connection point for the SPK_OUTB+ bootstrap capacitor, which is used to create a power supply for the high-side gate drive for SPK_OUTB+
DGND	17	G	-	Ground for digital circuitry (NOTE: This terminal should be connected to the system ground)
DR_CN	24	P	-	Negative pin for capacitor connection used in headphone amplifier/line driver charge pump
DR_CP	25	P	-	Positive pin for capacitor connection used in headphone amplifier/line driver charge pump
DR_INA-	18	AI	-	Negative differential input for channel A of headphone amplifier/line driver
DR_INA+	19	AI	-	Positive differential input for channel A of headphone amplifier/line driver
DR_INB-	31	AI	-	Negative differential input for channel B of headphone amplifier/line driver
DR_INB+	30	AI	-	Positive differential input for channel B of headphone amplifier/line driver
DR_MUTE	22	DI	-	Places the headphone amplifier/line driver in mute
DR_OUTA	20	AO	-	Output for channel A of headphone amplifier/line driver
DR_OUTB	29	AO	-	Output for channel B of headphone amplifier/line driver
DR_UVE	28	AI	-	Sense pin for under-voltage protection circuit for the headphone amplifier/line driver
DR_VSS	23	P	-	Negative power supply generated by charge pump from the DRVDD supply for ground centered headphone/line driver output
DRGND	21	G	-	Ground for headphone amplifier/line driver circuitry (NOTE: This terminal should be connected to the system ground)
DRGND	27	G	-	Ground for headphone amplifier/line driver circuitry (NOTE: This terminal should be connected to the system ground)
DRVDD	26	P	-	Power supply for internal headphone/line driver circuitry
DVDD	9	P	-	Power supply for the internal digital circuitry
FREQ/SDA	7	DI	Weak Pulldown	Dual function terminal that functions as an I²C data input pin in I²C Control Mode or as a Frequency Select terminal when in Hardware Control Mode.
GGND	47	G	-	Ground for gate drive circuitry (NOTE: This terminal should be connected to the system ground)
GVDD_REG	48	P	-	Voltage regulator derived from PVDD supply (NOTE: This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry)
LRCK	16	DI	Weak Pulldown	Serial Audio Port Word Clock. Word select clock for the digital signal that is active on the serial port's input data line
MCLK	13	DI	Weak Pulldown	Master Clock used for internal clock tree, sub-circuit/state machine, and Serial Audio Port clocking
PBTL/SCL	8	DI	Weak Pulldown	Dual function pin that functions as an I²C clock input terminal in Software Control Mode or configures the device to operate in pre-filter Parallel Bridge Tied Load (PBTL) mode when in Hardware Control Mode
PGND	36, 41	G	-	Ground for power device circuitry (NOTE: This terminal should be connected to the system ground)
PVDD	32, 33, 44, 45	P	-	Power supply for interal power circuitry
SCLK	14	DI	Weak Pulldown	Serial Audio Port Bit Clock. Bit clock for the digital signal that is active on the serial data port's input data line
SDIN	15	DI	Weak Pulldown	Serial Audio Port Serial Data In. Data line to the serial data port
SFT_CLIP	1	AI	-	Sense pin which sets the maximum output voltage before clipping when the soft clipper circuit is active
SPK_FAULT	5	DO	Open-Drain	Speaker amplifier fault terminal, which is pulled LOW when an internal fault occurs
SPK_GAIN0	10	DI	Weak Pulldown	Adjusts the LSB of the multi-bit gain of the speaker amplifier
SPK_GAIN1	11	DI	Weak Pulldown	Adjusts the MSB of the multi-bit gain of the speaker amplifier
SPK_SLEEP/ADR	12	DI	Weak Pullup	In Hardware Control Mode, places the speaker amplifier in sleep mode. In Software Control Mode, is used to determine the I²C Address of the device
SPK_OUTA-	40	AO	-	Negative pin for differential speaker amplifier output A
SPK_OUTA+	42	AO	-	Positive pin for differential speaker amplifier output A
SPK_OUTB-	37	AO	-	Negative pin for differential speaker amplifier output B
SPK_OUTB+	35	AO	-	Positive pin for differential speaker amplifier output B
SPK_SD	6	DI	-	Places the speaker amplifier in shutdown
VCOM	3	P	-	Bias voltage for internal PWM conversion block
PowerPAD™	-	G	-	Provides both electrical and thermal connection from the device to the board. A matching ground pad must be provided on the PCB and the device connected to it via solder. For proper electrical operation, this ground pad must be connected to the system ground.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Temperature	Ambient Operating Temperature, T_A	–25	85	°C
Temperature	Ambient Storage Temperature, T_S	–40	125	°C
Supply Voltage	AVDD Supply	–0.3	20	V
	PVDD Supply	–0.3	20	V
	DRVDD and DVDD Supply	–0.3	4	V
DVDD Referenced Digital Input Voltages	Digital Inputs referenced to DVDD supply	–0.5	DVDD + 0.5	V
DRVDD Referenced Digital Input Voltages	Digital Inputs referenced to DRVDD supply	–0.5	DRVDD + 0.5	V
Headphone Load	R_HP	12.8		Ω
Line Driver Load	R_LD	600		Ω
Speaker Amplifier Output Voltage	V_{SPK_OUTxx}, measured at the output pin	–0.3	22	V
Storage temperature range, T_stg		–40	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
T_A	Ambient Operating Temperature	–25		85	°C
AVDD	AVDD Supply	4.5		16.5	V
PVDD	PVDD Supply	4.5		16.5	V
DRVDD, DVDD	DRVDD and DVDD Supply	2.8		3.63	V
VIH_(DR)	Input Logic HIGH for DVDD and DRVDD Referenced Digital Inputs		DVDD		V
VIL_(DR)	Input Logic LOW for DVDD and DRVDD Referenced Digital Inputs		0		V
R_HP	Headphone Load	16			Ω
R_LD	Line Driver Load	1			Ω
R_{SPK (BTL)}	Minimum Speaker Load in BTL Mode	4			Ω
R_{SPK (PBTL)}	Minimum Speaker Load in PBTL Mode	2			Ω

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TAS5760LD		UNIT
		DCA [HTSSOP]	DCA [HTSSOP]
		48 PIN⁽²⁾	48 PIN⁽³⁾
θ_JA	Junction-to-ambient thermal resistance	60.3	30.2	°C/W
θ_JC(top)	Junction-to-case (top) thermal resistance	16	14.3	°C/W
θ_JB	Junction-to-board thermal resistance	12	12.7	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	0.6	°C/W
ψ_JB	Junction-to-board characterization parameter	11.9	12.7	°C/W
θ_JC(bottom)	Junction-to-case (bottom) thermal resistance	0.8	0.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) JEDEC Standard 2 Layer Board

(3) JEDEC Standard 4 Layer Board

6.5 Digital I/O Pins

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH1	Input Logic HIGH threshold for DVDD Referenced Digital Inputs	All digital pins except for DR_MUTE	70			%DVDD
V_IL1	Input Logic LOW threshold for DVDD Referenced Digital Inputs	All digital pins except for DR_MUTE			30	%DVDD
I_IH₁	Input Logic HIGH Current Level	All digital pins except for DR_MUTE			15	µA
I_IL₁	Input Logic LOW Current Level	All digital pins except for DR_MUTE			–15	µA
V_OH	Output Logic HIGH Voltage Level	I_OH = 2 mA	90			%DVDD
V_OL	Output Logic LOW Voltage Level	I_OH = -2 mA			10	%DVDD
V_IH2	Input Logic HIGH threshold for DRVDD Referenced Digital Inputs	For DR_MUTE Pin		60		%DRVDD
V_IL2	Input Logic LOW threshold for DRVDD Referenced Digital Inputs	For DR_MUTE Pin		40		%DRVDD
I_IH₂	Input Logic HIGH Current Level	For DR_MUTE Pin			1	µA
I_IL₂	Input Logic LOW Current Level	For DR_MUTE Pin			–1	µA

6.6 Master Clock

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
D_MCLK	Allowable MCLK Duty Cycle		45%	50%	55%
f_MCLK	MCLK Input Frequency				25	MHz
	Supported single-speed MCLK Frequencies	Values: 64, 128, 192, 256, 384, and 512	64		512	x f_s
	Supported double-speed MCLK Frequencies	Values: 64, 128, and 256	64		256	x f_s

6.7 Serial Audio Port

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
D_SCLK	Allowable SCLK Duty Cycle		45%	50%	55%
t_{H_L}	Time high and low, SCLK, LRCK, SDIN		10			ns
t_SU t_HLD	Setup and Hold time. LRCK, SDIN input to SCLK edge	Input t_RISE ≤ 1 ns, input t_FALL ≤ 1 ns			5	ns
		Input t_RISE ≤ 4 ns, input t_FALL ≤ 4 ns	8
		Input t_RISE ≤ 8 ns, input t_FALL ≤ 8 ns	12
t_RISE	Rise-time SCLK, LRCK, SDIN inputs				8	ns
t_FALL	Fall-time SCLK, LRCK, SDIN inputs				8	ns
f_S	Supported Input Sample Rates	Sample rates above 48kHz supported by "double speed mode," which is activated through the I²C control port	32		96	kHz
f_SCLK	Supported SCLK Frequencies	Values include: 32, 48, 64	32		64	f_S

6.8 Protection Circuitry

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	UNIT
OVE_RTHRES(PVDD)	PVDD Overvoltage Error Threshold	PVDD Rising	18	V
OVE_FTHRES(PVDD)	PVDD Overvoltage Error Threshold	PVDD Falling	17.3	V
UVE_FTHRES_(PVDD)	PVDD Undervoltage Error (UVE) Threshold	PVDD Falling	3.95	V
UVE_RTHRES(PVDD)	PVDD UVE Threshold (PVDD Rising)	PVDD Rising	4.15	V
OTE_THRES	Overtemperature Error (OTE) Threshold		150	°C
OTE_HYST	Overtemperature Error (OTE) Hysteresis		15	°C
OCE_THRES	Overcurrent Error (OCE) Threshold for each BTL Output	PVDD= 15V, T_A = 25 °C	7	A
DCE_THRES	DC Error (DCE) Threshold	PVDD= 12V, T_A = 25 °C	2.6	V
T_{SPK_FAULT}	Speaker Amplifier Fault Time Out period	DC Detect Error	650	ms
T_{SPK_FAULT}	Speaker Amplifier Fault Time Out period	OTE or OCP Fault	1.3	s
UVE_THRES_(DRVDD)	Undervoltage Error (UVE) Threshold for headphone and line driver amplifier	Sensed on DR_UVE pin	1.25	V
I_LIMIT(DR)	Current Sourcing Limit of the Headphone and line driver amplifier		68	mA

6.9 Speaker Amplifier in All Modes

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
AV₀₀	Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 00	Hardware Control Mode (Additional gain settings available in Software Control Mode)⁽¹⁾	25.2		dBV
AV₀₁	Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 01	Hardware Control Mode (Additional gain settings available in Software Control Mode)⁽¹⁾	28.6		dBV
AV₁₀	Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 10	Hardware Control Mode (Additional gain settings available in Software Control Mode)⁽¹⁾	31		dBV
AV₁₁	Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 11	(This setting places the device in Software Control Mode)	(Set via I²C)
\|VOS\|_{(SPK_AMP)}	Speaker Amplifier DC Offset	BTL, Worst case over voltage, gain settings		10	mV
\|VOS\|_{(SPK_AMP)}	Speaker Amplifier DC Offset	PBTL, Worst case over voltage, gain settings		15	mV
f_{SPK_AMP(0)}	Speaker Amplifier Switching Frequency when PWM_FREQ Pin = 0	(Hardware Control Mode. Additional switching rates available in Software Control Mode.)	16		f_S
f_{SPK_AMP(1)}	Speaker Amplifier Switching Frequency when PWM_FREQ Pin = 1	(Hardware Control Mode. Additional switching rates available in Software Control Mode.)	8		f_S
R_DS(ON)	On Resistance of Output MOSFET (both high-side and low-side)	PVDD = 15 V, TA = 25 °C, Die Only	120		mΩ
R_DS(ON)		PVDD= 15V, TA = 25 °C, Includes: Die, Bond Wires, Leadframe	150		mΩ
f_C	–3-dB Corner Frequency of High-Pass Filter	f_S = 44.1 kHz	3.7		Hz
		f_S = 48 kHz	4
		f_S = 88.2 kHz	7.4
		f_S = 96 kHz	8

(1) The digital boost block contributes +6dB of gain to this value. The audio signal must be kept below -6dB to avoid clipping the digital audio path.

6.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode

input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ICN_(SPK)	Idle Channel Noise	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, A-Weighted	-	66	-	µVrms
ICN_(SPK)	Idle Channel Noise	PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, A-Weighted	-	75	-	µVrms
P_O(SPK)	Maximum Instantaneous Output Power Per. Ch.	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 4Ω, THD+N = 0.1%,	-	14.2	-	W
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, THD+N = 0.1%	-	8	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 4Ω, THD+N = 0.1%,	-	21.9	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, THD+N = 0.1%	-	12.5	-	W
P_O(SPK)	Maximum Continuous Output Power Per. Ch.⁽¹⁾	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 4Ω, THD+N = 0.1%,	-	14	-	W
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, THD+N = 0.1%	-	8	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 4Ω, THD+N = 0.1%,	-	13.25	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, THD+N = 0.1%	-	12.5	-	W
SNR_(SPK)	Signal to Noise Ratio (Referenced to THD+N = 1%)	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, A-Weighted, -60dBFS Input	-	99.7	-	dB
SNR_(SPK)	Signal to Noise Ratio (Referenced to THD+N = 1%)	PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, A-Weighted, -60dBFS Input	-	98.2	-	dB
THD+N_(SPK)	Total Harmonic Distortion and Noise	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 4Ω, Po = 1 W	-	0.02%	-
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, Po = 1 W	-	0.03%	-
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 4Ω, Po = 1 W	-	0.03%	-
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, Po = 1 W	-	0.03%	-
X-Talk_(SPK)	Cross-talk (worst case between LtoR and RtoL coupling)	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, Input Signal 250 mVrms, 1kHz Sine	-	-92	-	dB
X-Talk_(SPK)	Cross-talk (worst case between LtoR and RtoL coupling)	PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, Input Signal 250 mVrms, 1kHz Sine	-	-93	-	dB

(1) The continuous power output of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on it by the system around it, such as the PCB configuration and the ambient operating temperature. The performance characteristics listed in this section are achievable on the TAS5760LD's EVM, which is representative of the poplular "2 Layers / 1oz Copper" PCB configuration in a size that is representative of the amount of area often provided to the amplifier section of popular consumer audio electronics. As can be seen in the instantaneous power portion of this table, more power can be delivered from the TAS5760LD if steps are taken to pull more heat out of the device. For instance, using a board with more layers or adding a small heatsink will result in an increase of continuous power, up to and including the instantaneous power level. This behavior can also been seen in the POUT vs. PVDD plots shown in the typical performance plots section of this data sheet.

6.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode

input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ICN	Idle Channel Noise	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, A-Weighted	-	69	-	µVrms
ICN	Idle Channel Noise	PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, A-Weighted	-	85	-	µVrms
P_O(SPK)	Maximum Instantaneous Output Power	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 2Ω, THD+N = 0.1%,	-	28.6	-	W
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 4Ω, THD+N = 0.1%,	-	15.9	-	W
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, THD+N = 0.1%	-	8.4	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 2Ω, THD+N = 0.1%,	-	43.2	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 4Ω, THD+N = 0.1%,	-	25	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, THD+N = 0.1%	-	13.3	-	W
P_O(SPK)	Maximum Continuous Output Power⁽¹⁾	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 2Ω, THD+N = 0.1%,	-	30	-	W
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 4Ω, THD+N = 0.1%,	-	15.9	-	W
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, THD+N = 0.1%	-	8.4	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 2Ω, THD+N = 0.1%,	-	28.5	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 4Ω, THD+N = 0.1%,	-	25	-	W
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, THD+N = 0.1%	-	13.3	-	W
SNR	Signal to Noise Ratio (Referenced to THD+N = 1%)	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, A-Weighted, -60dBFS Input	-	100.4	-	dB
SNR	Signal to Noise Ratio (Referenced to THD+N = 1%)	PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, A-Weighted, -60dBFS Input	-	99.5	-	dB
THD+N_(SPK)	Total Harmonic Distortion and Noise	PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 2Ω, Po = 1 W	-	0.03%	-
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 4Ω, Po = 1 W	-	0.02%	-
		PVDD = 12 V, SPK_GAIN[1:0] Pins = 00, R_SPK = 8Ω, Po = 1 W	-	0.02%	-
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 2Ω, Po = 1 W	-	0.03%	-
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 4Ω, Po = 1 W	-	0.02%	-
		PVDD = 15 V, SPK_GAIN[1:0] Pins = 01, R_SPK = 8Ω, Po = 1 W	-	0.02%	-

6.12 Headphone Amplifier and Line Driver

input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Input to Output Attenuation when muted			80		dB
\|VOS\|_(DR)	Output Offset Voltage of Headphone Amplifier and Line Driver			0.5		mV
f_CP	Charge Pump Switching Frequency		200	300	400	kHz
ICN_(HP)	Idle Channel Noise	R_(HP) = 32 Ω, A-Weighted		13		µVrms
ICN_(LD)	Idle Channel Noise	R_(LD) = 3 kΩ, A-Weighted		11		µVrms
Po_(HP)	Headphone Amplifier Output Power	R_(HP) = 16 Ω, THD+N = 1%, Outputs in Phase		40		mW
PSRR_(DR)	Power Supply Rejection Ratio of Headphone Amplifier and Line Driver			80		dB
SNR_(HP)	Signal to Noise Ratio	(Referenced to 25 mW Output Signal), R_(HP) = 16 Ω, A-Weighted		96		dB
SNR_(LD)	Signal to Noise Ratio	(Referenced to 2 Vrms Output Signal), R_(LD) = 3 kΩ, A-Weighted	90	105		dB
THD+N(HP)	Total Harmonic Distortion and Noise for the Headphone Amplifier	P_O(HP) = 10 mW		0.01%
THD+N_(LD)	Total Harmonic Distortion and Noise for the Line Driver	V_O(LD) = 2 Vrms		0.002%
Vo_(LD)	Line Driver Output Voltage	THD+N = 1%, R_(LD) = 3kΩ, Outputs in Phase	2	2.4		Vrms
X-Talk_(HP)	Cross-talk (worst case between LtoR and RtoL coupling)	P_O(HP) = 20 mW		–90		dB
X-Talk_(LD)	Cross-talk (worst case between LtoR and RtoL coupling)	Vo = 1 Vrms		–111		dB
Z_O(DR)	Output Impedance when muted	DR_MUTE = LOW		110		mΩ
I_MUTE(DR)	Current drawn from DRVDD supply in mute	DR_MUTE = LOW		12		mA
I_DRVDD(HP)	Current drawn from DRVDD supply with headphone	DR_MUTE = HIGH, P_O(HP) = 25 mW, Input = 1kHz		60		mA
I_DRVDD(LD)	Current drawn from DRVDD supply with line driver	DR_MUTE = HIGH, V_O(LD) = 2 Vrms, Input = 1kHz		12		mA

6.13 I²C Control Port

specifications are over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
C_L(I²C)	Allowable Load Capacitance for Each I²C Line			400	pF
f_SCL	Support SCL frequency	No Wait States		400	kHz
t_buf	Bus Free time between STOP and START conditions		1.3		µS
t_f(I²C)	Rise Time, SCL and SDA			300	ns
t_h1(I²C)	Hold Time, SCL to SDA		0		ns
t_h2(I²C)	Hold Time, START condition to SCL		0.6		µs
t_I²C(start)	I²C Startup Time			12	mS
t_r(I²C)	Rise Time, SCL and SDA			300	ns
t_su1(I²C)	Setup Time, SDA to SCL		100		ns
t_su2(I²C)	Setup Time, SCL to START condition		0.6		µS
t_su3(I²C)	Setup Time, SCL to STOP condition		0.6		µS
T_w(H)	Required Pulse Duration, SCL HIGH		0.6		µS
T_w(L)	Required Pulse Duration, SCL LOW		1.3		µS

6.14 Typical Idle, Mute, Shutdown, Operational Power Consumption

input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)

V_PVDD [V]	R_SPK [Ω]	SPEAKER AMPLIFIER STATE		I_PVDD+AVDD [mA]	I_DVDD [mA]	P_DISS [W]
6	4	f_{SPK_AMP}= 384kHz	Idle	23.48	3.73	0.15
	8		Idle	23.44	3.72	0.15
	4		Mute	23.53	3.72	0.15
	8		Mute	23.46	3.72	0.15
	4		Sleep	13.26	0.48	0.08
	8		Sleep	13.27	0.53	0.08
	4		Shutdown	0.046	0.04	0
	8		Shutdown	0.046	0.03	0
	4	f_{SPK_AMP} = 768kHz	Idle	30.94	3.71	0.2
	8		Idle	30.94	3.71	0.2
	4		Mute	29.37	3.71	0.19
	8		Mute	29.39	3.71	0.19
	4		Sleep	13.24	0.5	0.08
	8		Sleep	13.23	0.52	0.08
	4		Shutdown	0.046	0.03	0
	8		Shutdown	0.046	0.03	0
	4	f_{SPK_AMP} = 1152kHz	Idle	39.39	3.7	0.25
	8		Idle	39.43	3.7	0.25
	4		Mute	36.91	3.7	0.23
	8		Mute	36.9	3.69	0.23
	4		Sleep	13.17	0.53	0.08
	8		Sleep	13.13	0.45	0.08
	4		Shutdown	0.046	0.03	0
	8		Shutdown	0.046	0.03	0
12	4	f_{SPK_AMP}= 384kHz	Idle	32.95	3.74	0.41
	8		Idle	32.93	3.73	0.41
	4		Mute	32.98	3.73	0.41
	8		Mute	32.97	3.73	0.41
	4		Sleep	12.71	0.47	0.15
	8		Sleep	12.75	0.5	0.15
	4		Shutdown	0.053	0.04	0
	8		Shutdown	0.053	0.04	0
	4	f_{SPK_AMP} = 768kHz	Idle	44.84	3.73	0.55
	8		Idle	44.82	3.73	0.55
	4		Mute	42.71	3.72	0.52
	8		Mute	42.66	3.72	0.52
	4		Sleep	12.71	0.49	0.15
	8		Sleep	12.73	0.52	0.15
	4		Shutdown	0.063	0.03	0
	8		Shutdown	0.053	0.03	0
	4	f_{SPK_AMP} = 1152kHz	Idle	59.3	3.73	0.72
	8		Idle	59.3	3.73	0.72
	4		Mute	55.74	3.72	0.68
	8		Mute	55.74	3.72	0.68
	4		Sleep	12.67	0.49	0.15
	8		Sleep	12.61	0.43	0.15
	4		Shutdown	0.053	0.02	0
	8		Shutdown	0.053	0.03	0

6.15 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode)

At T_A = 25°C, f_{SPK_AMP} = 384 kHz, input signal is 1 kHz Sine, unless otherwise noted. Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless otherwise noted.

Thermal Limits are referenced to TAS5760xxEVM Rev D

Figure 1. Output Power vs PVDD

TAS5760LD G025_BTL_384_THDvsF_15V_SLOS781.png

PVDD = 12 V, P_OSPK = 1 W

Figure 3. THD+N vs Frequency

PVDD = 12 V, Both Channels Driven

Figure 5. THD+N vs Output Power

TAS5760LD G030_BTL_384_EFFvsPO_15V_8R_SLOS781.png

Figure 7. Efficiency vs Output Power

TAS5760LD G019_BTL_384_PVDD_PSRRvsF_SLOS781.png

Figure 9. PVDD PSRR vs Frequency

TAS5760LD G042_BTL_384_Idle_CurrentvsPVDD_Filterless_SLOS781.png

Figure 11. Idle Current Draw vs PVDD (Filterless)

TAS5760LD G022_BTL_384_Shutdown_CurrentvsPVDD_Filterless_SLOS781.png

Figure 13. Shutdown Current Draw vs PVDD (Filterless)

PVDD = 12 V, P_OSPK = 1 W

Figure 2. THD+N vs Frequency

TAS5760LD G026_BTL_384_ICNvsVDD_8R_SLOS781.png

Figure 4. Idle Channel Noise vs PVDD

TAS5760LD G029_BTL_384_THDNvsP0_15V_SLOS781.png

PVDD = 12 V, Both Channels Driven

Figure 6. THD+N vs Output Power

TAS5760LD G031_BTL_384_XTALKvsF_15V_4R_SLOS781.png

Figure 8. Crosstalk vs Frequency

TAS5760LD G020_BTL_384_DVDD_PSRRvsF_SLOS781.png

Figure 10. DVDD PSRR vs Frequency

TAS5760LD G023_BTL_384_Idle_CurrentvsPVDD_LCFilter_SLOS781.png

With LC Filter as shown on the EVM

Figure 12. Idle Current Draw vs PVDD

At T_A = 25°C, f_{SPK_AMP} = 768 kHz, input signal is 1 kHz Sine, unless otherwise noted.
Filter used for 8 Ω = 22 µH + 0.68 µF, Filter used for 6 Ω = 15 µH + 0.68 µF, Filter used for 4 Ω = 10 µH + 0.68 µF unless otherwise noted.