SLAS965D
September 2013 – October 2018
TAS5766M
,
TAS5768M
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Smart Amplifier Overview
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
AC Electrical Characteristics
6.7
Electrical Characteristics
6.8
Timing Requirements - I2C Bus Timing
6.9
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Smart SOA
7.3.2
Smart BASS
7.3.3
Smart Protection
7.3.4
Implementing a Real World Design
7.3.5
Modulation Schemes
7.3.5.1
BD-Modulation
7.3.5.2
1SPW-Modulation
7.4
Device Functional Modes
7.4.1
Device Protection System
7.4.1.1
Over Current Protection
7.4.1.2
Thermal Protection
7.4.1.3
DC Protection
7.4.2
Reset and System Clock Functions
7.4.2.1
Power-On Reset Function
7.4.2.2
System Clock Input
7.4.3
System Clock PLL Mode
7.4.4
Clock Generation and PLL
7.4.5
PLL Calculation
7.4.6
Audio Data Interface
7.4.6.1
Audio Serial Interface
7.4.6.2
PCM Audio Data Formats and Timing
7.4.7
TAS576xM Audio Processing Options
7.4.7.1
Overview
7.4.7.2
miniDSP Instruction Register
7.4.7.3
Digital Output
7.4.7.4
Software
7.4.7.5
Process Flow
7.4.7.6
Zero Data Detect
7.4.7.7
Power Save Modes
7.4.7.8
XSMT Pin (Soft Mute/Soft Un-Mute)
7.4.7.9
External Power Sense Undervoltage Protection Mode
7.4.7.10
Recommended Power Down Sequence
7.4.7.10.1
XSMT = 0
7.4.7.10.2
Clock Error Detect
7.4.7.10.3
Planned Shutdown
7.5
Programming
7.5.1
I2C Interface and Slave Address
7.5.2
Slave Address
7.5.3
Register Address Auto-Increment Mode
7.5.4
Packet Protocol
Table 18.
Read / Write Operation – Basic I2C Framework
7.5.5
Write Register
Table 19.
Write Operation
7.5.5.1
Read Register
Table 20.
Read Operation
7.6
Register Maps
8
Applications and Implementation
8.1
Application Information
8.1.1
External Component Selection Criteria
8.1.2
Component Selection Impact on Board Layout, Component Placement, and Trace Routing
8.1.3
Amplifier Output Filtering
8.2
Typical Applications
8.2.1
Stereo Application
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Gain Setting and Output Switch Frequency
8.2.1.2.2
Gain Setting and Supply Voltage
8.2.1.2.3
DAC to AMP AC Coupling
8.2.1.2.4
Bootstrap Capacitors
8.2.1.3
BTL Application Curves
8.2.2
Mono/PBTL Application
8.2.2.1
Design Requirements
8.2.2.2
PBTL Application Curves
8.2.3
QFN BTL Application Diagram
8.2.3.1
Design Requirements
9
Power Supply Recommendations
9.1
AVDD, DVDD, CPVDD Supply
9.2
GVDD Supply
9.3
PVCC, AVCC Power Supply
10
Layout
10.1
Layout Guidelines
10.2
Layout Examples
11
Register Map Information
11.1
Detailed Register Map Descriptions
11.1.1
Register Map Summary
11.1.2
Page 0 Registers
11.1.2.1
Page 0 / Register 1 (Hex 0x01)
11.1.2.2
Page 0 / Register 2 (Hex 0x02)
11.1.2.3
Page 0 / Register 3 (Hex 0x03)
11.1.2.4
Page 0 / Register 4 (Hex 0x04)
11.1.2.5
Page 0 / Register 7 (Hex 0x07)
11.1.2.6
Page 0 / Register 8 (Hex 0x08)
11.1.2.7
Page 0 / Register 9 (Hex 0x09)
11.1.2.8
Page 0 / Register 10 (Hex 0x0A)
11.1.2.9
Page 0 / Register 12 (Hex 0x0C)
11.1.2.10
Page 0 / Register 13 (Hex 0x0D)
11.1.2.11
Page 0 / Register 20 (Hex 0x14)
11.1.2.12
Page 0 / Register 21 (Hex 0x15)
11.1.2.13
Page 0 / Register 22 (Hex 0x16)
11.1.2.14
Page 0 / Register 23 (Hex 0x17)
11.1.2.15
Page 0 / Register 24 (Hex 0x18)
11.1.2.16
Page 0 / Register 27 (Hex 0x1B)
11.1.2.17
Page 0 / Register 28 (Hex 0x1C)
11.1.2.18
Page 0 / Register 29 (Hex 0x1D)
11.1.2.19
Page 0 / Register 30 (Hex 0x1E)
11.1.2.20
Page 0 / Register 32 (Hex 0x20)
11.1.2.21
Page 0 / Register 33 (Hex 0x21)
11.1.2.22
Page 0 / Register 34 (Hex 0x22)
11.1.2.23
Page 0 / Register 35 (Hex 0x23)
11.1.2.24
Page 0 / Register 36 (Hex 0x24)
11.1.2.25
Page 0 / Register 37 (Hex 0x25)
11.1.2.26
Page 0 / Register 40 (Hex 0x28)
11.1.2.27
Page 0 / Register 41 (Hex 0x29)
11.1.2.28
Page 0 / Register 42 (Hex 0x2A)
11.1.2.29
Page 0 / Register 43 (Hex 0x2B)
11.1.2.30
Page 0 / Register 44 (Hex 0x2C)
11.1.2.31
Page 0 / Register 59 (Hex 0x3B)
11.1.2.32
Page 0 / Register 65 (Hex 0x41)
11.1.2.33
Page 0 / Register 66 (Hex 0x42)
11.1.2.34
Page 0 / Register 82 (Hex 0x52)
11.1.2.35
Page 0 / Register 83 (Hex 0x53)
11.1.2.36
Page 0 / Register 84 (Hex 0x54)
11.1.2.37
Page 0 / Register 85 (Hex 0x55)
11.1.2.38
Page 0 / Register 86 (Hex 0x56)
11.1.2.39
Page 0 / Register 87 (Hex 0x57)
11.1.2.40
Page 0 / Register 90 (Hex 0x5A)
11.1.2.41
Page 0 / Register 91 (Hex 0x5B)
11.1.2.42
Page 0 / Register 92 (Hex 0x5C)
11.1.2.43
Page 0 / Register 93 (Hex 0x5D)
11.1.2.44
Page 0 / Register 94 (Hex 0x5E)
11.1.2.45
Page 0 / Register 95 (Hex 0x5F)
11.1.2.46
Page 0 / Register 108 (Hex 0x6C)
11.1.2.47
Page 0 / Register 118 (Hex 0x76)
11.1.2.48
Page 0 / Register 119 (Hex 0x77)
11.1.2.49
Page 0 / Register 120 (Hex 0x78)
11.1.2.50
Page 0 / Register 121 (Hex 0x79)
11.1.3
Page 1 Registers
11.1.3.1
Page 1 / Register 2 (Hex 0x02)
11.1.3.2
Page 1 / Register 5 (Hex 0x05)
11.1.3.3
Page 1 / Register 6 (Hex 0x06)
11.1.3.4
Page 1 / Register 7 (Hex 0x07)
11.1.3.5
Page 1 / Register 8 (Hex 0x08)
11.1.4
Page 44 Registers
11.1.4.1
Page 44 / Register 1 (Hex 0x01)
12
Device and Documentation Support
12.1
Related Links
12.2
Trademarks
12.3
Electrostatic Discharge Caution
12.4
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RMT|48
MPQF399A
DCA|48
MPDS044E
Thermal pad, mechanical data (Package|Pins)
DCA|48
PPTD218D
Orderable Information
slas965d_oa
slas965d_pm
1
Features
PurePath Smart Amp:
Optimizes and Protects Dynamic Loudspeakers
Bass Q-compensation and Frequency Extension: More Loudness, Bass Enhancement, Better Clarity and Higher Fidelity.
Thermal and Excursion Limitation.
Stereo Class-D Amplifier With:
Wide Power Supply Range: 4.5 V –26.4 V
Wide Load Range: 2 Ω – 8 Ω;
High output current: 2x 7.5 A
Peak output power 2x 50 W/4 Ω
Continuous Power: 2x 20 W w/o heat sink
Click and Pop free: Power, Mute and Standby ON/OFF
Low Output Noise: <60 µVrms at 12 V-supply, <90 µVrms at 24-V supply
Low THD+N: <0.02% at 1 W/4 Ω, 1 kHz
Thermal, Over-Current and Short-Circuit Protected
Configurable Digital Audio Processor.
Down Mixing and Custom EQ with 10 BiQuads
Digital Audio Interface: I
2
S or TDM input w.
44.1 kHz and 48 kHz FS
Configurable Digital Output
Multisegment DAC with Excellent Jitter Suppression
Integrated High-Performance Audio PLL
I
2
C control
48-pin PowerPAD™ HTSSOP or VQFN Package