SLOSEA8 December   2024 TAS5815

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  8. 6 Typical Characteristics
    1. 6.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
    2. 6.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
    3. 6.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
    4. 6.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Serial Audio Port - Data Formats and Bit Depths
      5. 7.3.5 Clock Halt Auto-recovery
      6. 7.3.6 Sample Rate on the Fly Change
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Low EMI Modes
        1. 7.4.3.1 Minimize EMI with Spread Spectrum
        2. 7.4.3.2 Minimize EMI with channel to channel phase shift
        3. 7.4.3.3 Minimize EMI with Multi-Devices PWM Phase Synchronization
      4. 7.4.4 Thermal Foldback
      5. 7.4.5 Device State Control
      6. 7.4.6 Device Modulation
        1. 7.4.6.1 BD Modulation
        2. 7.4.6.2 1SPW Modulation
        3. 7.4.6.3 Hybrid Modulation
      7. 7.4.7 Load Detect
        1. 7.4.7.1 Short Load Detect
        2. 7.4.7.2 Open Load Detect
    5. 7.5 Programming and Control
      1. 7.5.1 I2C Serial Communication Bus
      2. 7.5.2 Target Address
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Random Read
        3. 7.5.2.3 Sequential Write
        4. 7.5.2.4 Sequential Read
        5. 7.5.2.5 DSP Memory Book, Page and BQ update
        6. 7.5.2.6 Example Use
        7. 7.5.2.7 Checksum
          1. 7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.2.7.2 Exclusive or (XOR) Checksum
      3. 7.5.3 Control via Software
        1. 7.5.3.1 Startup Procedures
        2. 7.5.3.2 Shutdown Procedures
        3. 7.5.3.3 Protection and Monitoring
          1. 7.5.3.3.1 Overcurrent Shutdown (OCSD)
          2. 7.5.3.3.2 DC Detect
          3. 7.5.3.3.3 Device Over Temperature Protection
          4. 7.5.3.3.4 Over Voltage Protection
          5. 7.5.3.3.5 Under Voltage Protection
          6. 7.5.3.3.6 Clock Fault
  10. 8 Register Maps
    1. 8.1 CONTROL PORT Registers
  11. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Bootstrap Capacitors
      2. 9.1.2 Inductor Selections
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Application
      1. 9.2.1 2.0 (Stereo BTL) System
        1. 9.2.1.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step 1: Hardware Integration
        2. 9.2.2.2 Step 2: Speaker Tuning
        3. 9.2.2.3 Step 3: Software Integration
      3. 9.2.3 MONO (PBTL) System
        1. 9.2.3.1 Design Requirements
      4. 9.2.4 Advanced 2.1 System (Two TAS5815 Devices)
  12. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  13. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
          2. 11.1.3.2.2 Solder Stencil
    2. 11.2 Layout Example
  14. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  15. 13Revision History
  16. 14Mechanical and Packaging Information
    1. 14.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.5.3.3.5 Under Voltage Protection

Once the PVDD voltage drop below the UVETHRES(PVDD) (4 V Typical), device will set the output driver from Play mode to Hi-Z mode. Under voltage fault reported by GLOBAL_FAULT1 (0x71) register in Book0/Page0. Once PVDD rise above 4.25 V (Typical), device will come back to Play mode. But this bit still keeps 1 unless clear it by FAULT_CLEAR (0x78) register in Book0/Page0 manually.