SLASEX7A June 2021 – December 2021 TAS5828M
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS , SCLK , and SDIN. SCLK is the serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio interface. Serial data is clocked into the TAS5828M device with SCLK. The LRCLK/FS pin is the serial audio left/right word clock or frame sync when the device is operated in TDM Mode.
FORMAT | DATA BITS | MAXIMUM LRCLK/FS FREQUENCY (kHz) | SCLK RATE (fS) |
---|---|---|---|
I2S/LJ/RJ | 32, 24, 20, 16 | 32 to 192 | 64, 32 |
TDM | 32, 24, 20, 16 | 32 | 128 |
44.1,48 | 128,256,512 | ||
96 | 128,256 | ||
192 | 128 |
When Clock halt, non-supported SCLK to LRCLK(FS) ratio is detected, the device reports Clock Error in Register 113 (Register Address 0x71).