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  • TAS6424-Q1 75-W,​​​ 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier With Load-Dump Protection and I2C Diagnostics

    • SLOS870B September   2016  – October 2017 TAS6424-Q1

      PRODUCTION DATA.  

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  • TAS6424-Q1 75-W,​​​ 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier With Load-Dump Protection and I2C Diagnostics
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter measurement Information
  9. 9 Detailed description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Audio Port
        1. 9.3.1.1 I2S Mode
        2. 9.3.1.2 Left-Justified Timing
        3. 9.3.1.3 Right-Justified Timing
        4. 9.3.1.4 TDM Mode
        5. 9.3.1.5 Supported Clock Rates
        6. 9.3.1.6 Audio-Clock Error Handling
      2. 9.3.2  High-Pass Filter
      3. 9.3.3  Volume Control and Gain
      4. 9.3.4  High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5  Gate Drive
      6. 9.3.6  Power FETs
      7. 9.3.7  Load Diagnostics
        1. 9.3.7.1 DC Load Diagnostics
        2. 9.3.7.2 Line Output Diagnostics
        3. 9.3.7.3 AC Load Diagnostics
      8. 9.3.8  Protection and Monitoring
        1. 9.3.8.1 Overcurrent Limit (ILIMIT)
        2. 9.3.8.2 Overcurrent Shutdown (ISD)
        3. 9.3.8.3 DC Detect
        4. 9.3.8.4 Clip Detect
        5. 9.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 9.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 9.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
        8. 9.3.8.8 Overvoltage (OV) and Load Dump
      9. 9.3.9  Power Supply
        1. 9.3.9.1 Vehicle-Battery Power-Supply Sequence
        2. 9.3.9.2 Boosted Power-Supply Sequence
      10. 9.3.10 Hardware Control Pins
        1. 9.3.10.1 FAULT
        2. 9.3.10.2 WARN
        3. 9.3.10.3 MUTE
        4. 9.3.10.4 STANDBY
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes and Faults
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Communication Bus
      2. 9.5.2 I2C Bus Protocol
      3. 9.5.3 Random Write
      4. 9.5.4 Sequential Write
      5. 9.5.5 Random Read
      6. 9.5.6 Sequential Read
    6. 9.6 Register Maps
      1. 9.6.1  Mode Control Register (address = 0x00) [default = 0x00]
      2. 9.6.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 9.6.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 9.6.4  SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
      5. 9.6.5  Channel State Control Register (address = 0x04) [default = 0x55]
      6. 9.6.6  Channel 1 Through 4 Volume Control Registers (address = 0x05-0x088) [default = 0xCF]
      7. 9.6.7  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      8. 9.6.8  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      9. 9.6.9  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      10. 9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      11. 9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      12. 9.6.12 DC Load Diagnostics Report 3—Line Output—Register (address = 0x0E) [default = 0x00]
      13. 9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
      14. 9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
      15. 9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
      16. 9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
      17. 9.6.17 Warnings Register (address = 0x13) [default = 0x20]
      18. 9.6.18 Pin Control Register (address = 0x14) [default = 0xFF]
      19. 9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      20. 9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      21. 9.6.21 AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17-0x1A) [default = 0x00]
      22. 9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
      23. 9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
      24. 9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
      25. 9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1C) [default = 0x00]
      26. 9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      27. 9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
      28. 9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
      29. 9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
      30. 9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
      31. 9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 AM-Radio Band Avoidance
      2. 10.1.2 Parallel BTL Operation (PBTL)
      3. 10.1.3 Demodulation Filter Design
      4. 10.1.4 Line Driver Applications
    2. 10.2 Typical Applications
      1. 10.2.1 BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Power Supplies
        3. 10.2.1.3 Communication
        4. 10.2.1.4 Detailed Design Procedure
          1. 10.2.1.4.1 Hardware Design
          2. 10.2.1.4.2 Digital Input and the Serial Audio Port
          3. 10.2.1.4.3 Bootstrap Capacitors
          4. 10.2.1.4.4 Output Reconstruction Filter
        5. 10.2.1.5 Application Curves
      2. 10.2.2 PBTL Application
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 Detailed Design Procedure
        2. 10.2.2.2 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Electrical Connection of Thermal pad and Heat Sink
      2. 12.1.2 EMI Considerations
      3. 12.1.3 General Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • DKQ|56
    • MPDS378A
Thermal pad, mechanical data (Package|Pins)
  • DKQ|56
    • PPTD313E
Orderable Information
  • slos870b_oa
  • slos870b_pm
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DATA SHEET

TAS6424-Q1 75-W,​​​ 2-MHz Digital Input 4-Channel Automotive Class-D Audio Amplifier With Load-Dump Protection and I2C Diagnostics

1 Features

  • Advanced Load Diagnostics
    • Runs without Input Clocks
    • AC Diagnostic for Tweeter Detection with Impedance and Phase Response
  • Easy to meet CISPR25-L5 EMC Specification
  • Qualified for Automotive Applications
  • Audio Inputs
    • 4 Channel I2S or 4/8-Channel TDM Input
    • Input Sample Rates: 44.1 kHz, 48 kHz, 96 kHz
    • Input Formats: 16-bit to 32-bit I2S, and TDM
  • Audio Outputs
    • Four-Channel Bridge-Tied Load (BTL), With Option of Parallel BTL (PBTL)
    • Up to 2.1-MHz Output Switching Frequency
    • 75 W, 10% THD Into 4 Ω at 25 V
    • 45 W, 10% THD Into 2 Ω at 14.4 V
    • 150 W, 10% THD Into 2 Ω at 25 V PBTL
  • Audio Performance Into 4 Ω at 14.4 V
    • THD+N < 0.03% at 1 W
    • 42-µVRMS Output Noise
    • –90-dB Crosstalk
  • Load Diagnostics
    • Output Open and Shorted Load
    • Output-to-Battery or Ground Shorts
    • Line Output Detection Up to 6 kΩ
    • Host-Independent Operation
    • Programmability for Flexible Production Line Testing
  • Protection
    • Output Current Limiting
    • Output Short Protection
    • 40-V Load Dump
    • Open Ground and Power Tolerant
    • DC Offset
    • Overtemperature
    • Undervoltage and Overvoltage
  • General Operation
    • 4.5-V to 26.4-V Supply voltage
    • I2C Control With 4 Address Options
    • Clip Detection and Thermal Warning

2 Applications

  • Automotive Head Units
  • Automotive External Amplifier Modules

3 Description

The TAS6424-Q1 device is a Four-channel digital-input Class-D audio amplifier that implements a 2.1 MHz PWM switching frequency that enables a cost-optimized solution in a very small PCB size, full operation down to 4.5 V for start/stop events, and exceptional sound quality with up to 40 kHz audio bandwidth

The TAS6424-Q1 Class-D audio amplifier is designed for use in automotive head units and external amplifier modules. The device provides four channels at 27 W into 4 Ω at 10% THD+N and 45 W into 2 Ω at 10% THD+N from a 14.4-V supply and 75 W into 4 Ω at 10% THD+N from a 25-V supply. The Class-D topology dramatically improves efficiency over traditional linear amplifier solutions. The output switching frequency can be set either above the AM band, which eliminates the AM-band interference and reduces output filter size and cost, or below AM band to optimize efficiency.

For a pin compatible two-channel amplifier, see the TAS6422-Q1

The device is offered in a 56-pin HSSOP PowerPAD™ package with the exposed thermal pad up.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TAS6424-Q1 HSSOP (56) 18.41 mm × 7.49 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

PCB AREA

TAS6424-Q1 front_slos870.gif

4 Revision History

Changes from A Revision (October 2016) to B Revision

  • Changed the Features and Description sections for better Product Folder visibilityGo

Changes from * Revision (September 2016) to A Revision

  • Released the full version of the data sheet Go

5 Device Comparison Table

PART NUMBER INPUT TYPE CHANNEL COUNT POWER-SUPPLY VOLTAGE RANGE OUTPUT CURRENT LIMIT MAXIMUM PWM FREQUENCY
TAS6424-Q1 Digital 4 4.5 V to 26.4 V 6.5 A 2.1 MHz
TAS5414C-Q1 Analog, Single-Ended 4 5.6 V to 24 V 12.7 A 500 kHz
TAS5424C-Q1 Analog, Differential 4 5.6 v to 24 V 12.7 A 500 kHz

6 Pin Configuration and Functions

DKQ Package
56-Pin HSSOP With Exposed Thermal Pad
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
AREF 4 PWR VREG and VCOM bypass capacitor return
AVDD 8 PWR Voltage regulator bypass
AVSS 7 PWR AVDD bypass capacitor return
BST_1M 31 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_1P 35 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_2M 37 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_2P 41 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_3M 44 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_3P 48 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_4M 50 PWR Bootstrap capacitor connection pins for high-side gate driver
BST_4P 54 PWR Bootstrap capacitor connection pins for high-side gate driver
FAULT 26 DO Reports a fault (active low, open drain), 100-kΩ internal pullup resistor
FSYNC 14 DI Audio frame clock input
GND 1 GND Ground
11
17
18
28
33
36
39
46
49
52
GVDD 9 PWR Gate drive voltage regulator for channel 3 and 4, derived from VBAT input pin.
10 Gate drive voltage regulator for channel 1 and 2, derived from VBAT input pin.
I2C_ADDR0 22 DI I2C address pins
I2C_ADDR1 23
MCLK 12 DI Audio master clock input
MUTE 25 DI Mutes the device outputs (active low), 100-kΩ internal pulldown resistor
OUT_1M 32 NO Negative output for the channel
OUT_1P 34 PO Positive output for the channel
OUT_2M 38 NO Negative output for the channel
OUT_2P 40 PO Positive output for the channel
OUT_3M 45 NO Negative output for the channel
OUT_3P 47 PO Positive output for the channel
OUT_4M 51 NO Negative output for the channel
OUT_4P 53 PO Positive output for the channel
PVDD 2 PWR PVDD voltage input (can be connected to battery)
29
30
42
43
55
56
SCL 20 DI I2C clock input
SCLK 13 DI Audio bit and serial clock input
SDA 21 DI/O I2C data input and output
SDIN1 15 DI TDM data input and audio I2S data input for channels 1 and 2
SDIN2 16 DI Audio I2S data input for channels 3 and 4
STANDBY 24 DI Enables low power standby state (active Low), 100-kΩ internal pulldown resistor
VBAT 3 PWR Battery voltage input
VCOM 6 PWR Bias voltage
VDD 19 PWR 3.3-V external supply voltage
VREG 5 PWR Voltage regulator bypass
WARN 27 DO Clip and overtemperature warning (active low, open drain), 100-kΩ internal pullup resistor
Thermal Pad — GND Provides both electrical and thermal connection for the device. Heatsink must be connected to GND.
(1) GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output, DI/O = digital input and output, NC = no connection

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
PVDD, VBAT DC supply voltage relative to GND –0.3 30 V
VMAX Transient supply voltage: PVDD, VBAT t ≤ 400 ms exposure –1 40 V
VRAMP Supply-voltage ramp rate: PVDD, VBAT 75 V/ms
VDD DC supply voltage relative to GND –0.3 3.5 V
IMAX Maximum current per pin (PVDD, VBAT, OUT_xP, OUT_xM, GND) 8 A
IMAX_PULSED Pulsed supply current per PVDD pin (one shot) t < 100 ms 12 A
VLOGIC Input voltage for logic pins (SCL, SDA, SDIN1, SDIN2, MCLK, BCLK, LRCLK, MUTE, STANDBY, I2C_ADDRx) –0.3 VDD + 0.5 V
VGND Maximum voltage between GND pins –0.3 0.3 V
TJ Maximum operating junction temperature –55 150 °C
Tstg Storage temperature –55 150 °C

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100–002(1) ±3000 V
Charged-device model (CDM), per AEC Q100–011 All pins ±500
Corner pins (1, 28, 29 and 56) ±1000
(1) AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
PVDD Output FET supply voltage Relative to GND 4.5 26.4 V
VBAT Battery supply voltage input Relative to GND 4.5 14.4 18 V
VDD DC logic supply Relative to GND 3.0 3.3 3.5 V
TA Ambient temperature –40 125 °C
TJ Junction temperature An adequate thermal design is required –40 150 °C
RL Nominal speaker load impedance BTL Mode 2 4 Ω
PBTL Mode 1 2
RPU_I2C I2C pullup resistance on SDA and SCL pins 1 4.7 10 kΩ
CBypass External capacitance on bypass pins Pin 2, 3, 5, 6, 8, 9, 10, 19 1 µF
COUT External capacitance to GND on OUT pins Limit set by DC-diagnostic timing 1 3.3 µF
LO Output filter inductance Minimum inductance at ISD current levels 1 µH

7.4 Thermal Information

THERMAL METRIC(1) TAS6424-Q1(2) TAS6424-Q1(3) UNIT
DKQ (HSSOP) DKQ (HSSOP)
56 PINS 56 PINS
RθJA Junction-to-ambient thermal resistance — — °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.7 1.1 °C/W
RθJB Junction-to-board thermal resistance — — °C/W
ψJT Junction-to-top characterization parameter — — °C/W
ψJB Junction-to-board characterization parameter 10 10 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) JEDEC Standard 4 Layer PCB.
(3) Measured using the TAS6424-Q1 EVM layout and heat sink. The device is not intended to be used without a heat sink.

7.5 Electrical Characteristics

Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79 and Figure 82
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
IPVDD_IDLE PVDD idle current All channels playing, no audio input 75 90 mA
IVBAT_IDLE VBAT idle current All channels playing, no audio input 90 100 mA
IPVDD_STBY PVDD standby current STANDBYActive, VDD = 0 V 1 10 μA
IVBAT_STBY VBAT standby current STANDBYActive, VDD = 0 V 4 10 μA
IVDD VDD supply current All channels playing, –60-dB signal 15 18 mA
OUTPUT POWER
PO_BTL Output power per channel, BTL 4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 20 22 W
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 25 27
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 38 40
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 42 45
4 Ω, PVDD = 25 V, THD+N = 1%, TC = 75°C 50 55
4 Ω, PVDD = 25 V, THD+N = 10%, TC = 75°C 70 75
PO_PBTL Output power per channel in parallel mode, PBTL 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 35 40 W
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 45 50
1 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 72 80
1 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 80 90
2 Ω, PVDD = 25 V, THD+N = 1%, TC = 75°C 98 120
2 Ω, PVDD = 25 V, THD+N = 10%, TC = 75°C 138 150
EFFP Power efficiency 4 channels operating, 25-W output power/ch 4-Ω load, PVDD = 14.4 V, TC = 25°C, including indcutor losses(1) 86%
AUDIO PERFORMANCE
Vn Output noise voltage Zero input, A-weighting, gain level 1, PVDD = 14.4 V 42 μV
Zero input, A-weighting, gain level 2, PVDD = 14.4 V 55
Zero input, A-weighting, gain level 3, PVDD = 18 V 67
Zero input, A-weighting, gain level 4, PVDD = 25 V 85
GAIN Peak output voltage/dBFS Gain level 1, Register 0x01, bit 1-0 = 00 7.5 V/FS
Gain level 2, Register 0x01, bit 1-0 = 01 15
Gain level 3, Register 0x01, bit 1-0 = 10 21
Gain level 4, Register 0x01, bit 1-0 = 11 29
Crosstalk Channel crosstalk PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz –90 –75 dB
PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz 75 dB
THD+N Total harmonic distortion + noise 0.02% 0.05%
GCH Channel-to-channel gain variation –0.5 0 0.5 dB
LINE OUTPUT PERFORMANCE
Vn_LINEOUT LINE output noise voltage Zero input, A-weighting, channel set to LINE MODE 42 μV
VO_LINEOUT LINE output voltage 0-dB input, channel set to LINE MODE 5.5 VRMS
THD+N Line output total harmonic distortion + noise VO = 2 VRMS , channel set to LINE MODE 0.01% 0.03%
DIGITAL INPUT PINS
VIH Input logic level high 70 %VDD
VIL Input logic level low 30 %VDD
IIH Input logic current, high VI = VDD 15 µA
IIL Input logic current, low VI = 0 –15 µA
PWM OUTPUT STAGE
RDS(on) FET drain-to-source resistance Not including bond wire and package resistance 90 mΩ
OVERVOLTAGE (OV) PROTECTION
VPVDD_OV PVDD overvoltage shutdown 27.0 27.8 28.8 V
VPVDD_OV_HYS PVDD overvoltage shutdown hysteresis 0.8 V
VVBAT_OV VBAT overvoltage shutdown 19.3 20 22 V
VVBAT_OV_HYS VBAT overvoltage shutdown hysteresis 0.6 V
UNDERVOLTAGE (UV) PROTECTION
VBATUV VBAT undervoltage shutdown 4 4.5 V
VBATUV_HYS VBAT undervoltage shutdown hysteresis 0.2 V
PVDDUV PVDD undervoltage shutdown 4 4.5 V
PVDDUV_HYS PVDD undervoltage shutdown hysteresis 0.2 V
BYPASS VOLTAGES
VGVDD Gate drive bypass pin voltage 7 V
VAVDD Analog bypass pin voltage 6 V
VVCOM Common bypass pin voltage 2.5 V
VVREG Regulator bypass pin voltage 5.5 V
POWER-ON RESET (POR)
VPOR VDD voltage for POR 2.1 2.7 V
VPOR_HY VDD POR recovery hysteresis voltage 0.5 V
OVERTEMPERATURE (OT) PROTECTION
OTW(i) Channel overtemperature warning 150 °C
OTSD(i) Channel overtemperature shutdown 175 °C
OTW Global junction overtemperature warning Set by register 0x01 bit 5-6, default value 130 °C
OTSD Global junction overtemperature shutdown 160 °C
OTHYS Overtemperature hysteresis 15 °C
LOAD OVER CURRENT PROTECTION
ILIM Overcurrent cycle-by-cycle limit OC Level 1 4 4.8 A
OC Level 2 6 6.5
ISD Overcurrent shutdown OC Level 1, Any short to supply, ground, or other channels 7 A
OC Level 2, Any short to supply, ground, or other channels 9
MUTE MODE
GMUTE Output attenuation 100 dB
CLICK AND POP
VCP Output click and pop voltage ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z 7 mV
DC OFSET
VOFFSET Output offset voltage 2 5 mV
DC DETECT
DCFAULT Output DC fault protection 2 2.5 V
DIGITAL OUTPUT PINS
VOH Output voltage for logic level high I = ±2 mA 90 %VDD
VOL Output voltage for logic level low I = ±2 mA 10 %VDD
tDELAY_CLIPDET Signal delay when output clipping detected 20 μs
LOAD DIAGNOSTICS
S2P Maximum resistance to detect a short from OUT pins to PVDD 500 Ω
S2G Maximum resistance to detect a short from OUT pins to ground 200 Ω
SL Shorted load detection tolerance Other channels in Hi-Z ±0.5 Ω
OL Open load Other channels in Hi-Z 40 70 Ω
TDC_DIAG DC diagnostic time All 4 Channels 230 ms
LO Line output 6 kΩ
TLINE_DIAG Line output diagnostic time 40 ms
ACIMP AC impedance accuracy Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω, 25%
Offset ±0.5 Ω
TAC_DIAG AC diagnostic time All 4 Channels 520 ms
I2C_ADDR PINS
tI2C_ADDR Time delay needed for I2C address set-up 300 μs
  1. Tested with Output Inductor DFEG7030D-3R3M.

7.6 Timing Requirements

Test conditions (unless otherwise noted): TC = 25 °C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, PO = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings, see Figure 79 and Figure 82
MIN TYP MAX UNIT
I2C CONTROL PORT (See Figure 42)
tBUS Bus free time between start and stop conditions 1.3 μs
tHOLD1 Hold time, SCL to SDA 0 ns
tHOLD2 Hold time, start condition to SCL 0.6 μs
tSTART I2C startup time after VDD power on reset 12 ms
tRISE Rise time, SCL and SDA 300 ns
tFALL Fall time, SCL and SDA 300 ns
tSU1 Setup, SDA to SCL 100 ns
tSU2 Setup, SCL to start condition 0.6 μs
tSU3 Setup, SCL to stop condition 0.6 μs
tW(H) Required pulse duration SCL High 0.6 μs
tW(L) Required pulse duration SCL Low 1.3 μs
SERIAL AUDIO PORT (See Figure 36)
DMCLK, DSCLK Allowable input clock duty cycle 45% 50% 55%
ƒMCLK Supported MCLK frequencies: 128, 256, or 512 128 512 xFS
ƒMCLK_Max Maximum frequency 25 MHz
tSCY SCLK pulse cycle time 40 ns
tSCL SCLK pulse-with LOW 16 ns
tSCH SCLK pulse-with HIGH 16 ns
trise/fall Rise and fall time 4 ns
tSF SCLK rising edge to FSYNC edge 8 ns
tFS FSYNC rising edge to SCLK edge 8 ns
tDS DATA set-up time 8 ns
tDH DATA hold time 8 ns
ci Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1, SDIN2 10 pF
TLA Latency from input to output measured in FSYNC sample count FSYNC = 44.1 kHz or 48 kHz 30
FSYNC = 96 kHz 12

7.7 Typical Characteristics

TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.11 MHz, AES17 filter, default I2C settings, see Figure 79 and Figure 82 (unless otherwise noted)
TAS6424-Q1 D002_SLOS870.gif
PO = 1 W
Figure 1. Crosstalk vs Frequency
TAS6424-Q1 D024_SLOS870.gif
PO = 1 W
Figure 3. VBAT PSRR vs Frequency
TAS6424-Q1 D006_SLOS870.gif
PO = 1 W 2.11-MHz fSW
Figure 5. THD+N vs Frequency
TAS6424-Q1 D008_SLOS870.gif
PO = 1 W 24 V 2.11-MHz fSW
Figure 7. THD+N vs Frequency
TAS6424-Q1 D010_SLOS870.gif
2.11-MHz fSW
Figure 9. THD+N vs Power
TAS6424-Q1 D012_SLOS870.gif
24 V 2.11-MHz fSW
Figure 11. THD+N vs Power
TAS6424-Q1 D014_SLOS870.gif
10% THD 2.11-MHz fSW
Figure 13. Output Power vs Supply Voltage
TAS6424-Q1 D016_SLOS870.gif
A-weighted Noise 2.11-MHz fSW
Figure 15. Noise vs Supply voltage
TAS6424-Q1 D020_SLOS870.gif
4 Ω 2.1-MHz fSW
Figure 17. Power Efficiency vs Output Power
TAS6424-Q1 D018_SLOS870.gif
2 Ω 2.1-MHz fSW
Figure 19. Power Efficiency vs Output Power
TAS6424-Q1 D026_SLOS870.gif
Figure 21. VBAT Current vs Voltage
TAS6424-Q1 D028_SLOS870.gif
1 W 384-kHz fSW
Figure 23. PBTL THD+N vs Frequency
TAS6424-Q1 D030_SLOS870.gif
PO = 1 W 384-kHz fSW 24-V PVDD
Figure 25. PBTL THD+N vs Frequency
TAS6424-Q1 D032_SLOS870.gif
384-kHz fSW
Figure 27. PBTL THD+N vs Power
TAS6424-Q1 D034_SLOS870.gif
384-kHz fSW
Figure 29. PBTL THD+N vs Power
TAS6424-Q1 D036_SLOS870.gif
384-kHz fSW
Figure 31. Output Power vs Voltage
TAS6424-Q1 D038_SLOS870.gif
384-kHz fSW
Figure 33. Power Dissipation vs Output Power
TAS6424-Q1 D022_SLOS870.gif
PO = 1 W
Figure 2. PVDD PSRR vs Frequency
TAS6424-Q1 D005_SLOS870.gif
PO = 1 W 384-kHz fSW
Figure 4. THD+N vs Frequency
TAS6424-Q1 D007_SLOS870.gif
PO = 1 W 24 V 384-kHz fSW
Figure 6. THD+N vs Frequency
TAS6424-Q1 D009_SLOS870.gif
384-kHz fSW
Figure 8. THD+N vs Power
TAS6424-Q1 D011_SLOS870.gif
24 V 384-kHz fSW
Figure 10. THD+N vs Power
TAS6424-Q1 D013_SLOS870.gif
10% THD 384-kHz fSW
Figure 12. Output Power vs Supply Voltage
TAS6424-Q1 D015_SLOS870.gif
A-weighted Noise 384-kHz fSW
Figure 14. Noise vs Supply Voltage
TAS6424-Q1 D019_SLOS870.gif
4 Ω 384-kHz fSW
Figure 16. Power Efficiency vs Output Power
TAS6424-Q1 D017_SLOS870.gif
2 Ω 384-kHz fSW
Figure 18. Power Efficiency vs Output Power
TAS6424-Q1 D025_SLOS870.gif
Figure 20. PVDD Current vs Voltage
TAS6424-Q1 D027_SLOS870.gif
Figure 22. PVDD Standby Current vs Voltage
TAS6424-Q1 D029_SLOS870.gif
PO = 1 W 2.1-MHz fSW
Figure 24. PBTL THD+N vs Frequency
TAS6424-Q1 D031_SLOS870.gif
Po = 1 W 2.1-MHz fSW 24-V PVDD
Figure 26. PBTL THD+N vs Frequency
TAS6424-Q1 D033_SLOS870.gif
2.1-MHz fSW
Figure 28. PBTL THD+N vs Power
TAS6424-Q1 D035_SLOS870.gif
2.1-MHz fSW 24-V PVDD
Figure 30. PBTL THD+N vs Power
TAS6424-Q1 D037_SLOS870.gif
2.1-MH fSW
Figure 32. Output Power vs Voltage
TAS6424-Q1 D039_SLOS870.gif
2.1-MHz fSW
Figure 34. Power Dissipation vs Output Power

 
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