SLOS948 February   2019 TAS6424M-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     PCB AREA
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Audio Port
        1. 9.3.1.1 I2S Mode
        2. 9.3.1.2 Left-Justified Timing
        3. 9.3.1.3 Right-Justified Timing
        4. 9.3.1.4 TDM Mode
        5. 9.3.1.5 Supported Clock Rates
        6. 9.3.1.6 Audio-Clock Error Handling
      2. 9.3.2  High-Pass Filter
      3. 9.3.3  Volume Control and Gain
      4. 9.3.4  High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5  Gate Drive
      6. 9.3.6  Power FETs
      7. 9.3.7  Load Diagnostics
        1. 9.3.7.1 DC Load Diagnostics
        2. 9.3.7.2 Line Output Diagnostics
        3. 9.3.7.3 AC Load Diagnostics
          1. 9.3.7.3.1 Impedance Magnitude Measurement
          2. 9.3.7.3.2 Impedance Phase Reference Measurement
          3. 9.3.7.3.3 Impedance Phase Measurement
      8. 9.3.8  Protection and Monitoring
        1. 9.3.8.1 Overcurrent Limit (ILIMIT)
        2. 9.3.8.2 Overcurrent Shutdown (ISD)
        3. 9.3.8.3 DC Detect
        4. 9.3.8.4 Clip Detect
        5. 9.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 9.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 9.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
        8. 9.3.8.8 Overvoltage (OV) and Load Dump
      9. 9.3.9  Power Supply
        1. 9.3.9.1 Vehicle-Battery Power-Supply Sequence
        2. 9.3.9.2 Boosted Power-Supply Sequence
      10. 9.3.10 Hardware Control Pins
        1. 9.3.10.1 FAULT
        2. 9.3.10.2 WARN
        3. 9.3.10.3 MUTE
        4. 9.3.10.4 STANDBY
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes and Faults
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Communication Bus
      2. 9.5.2 I2C Bus Protocol
      3. 9.5.3 Random Write
      4. 9.5.4 Sequential Write
      5. 9.5.5 Random Read
      6. 9.5.6 Sequential Read
    6. 9.6 Register Maps
      1. 9.6.1  Mode Control Register (address = 0x00) [default = 0x00]
        1. Table 10. Mode Control Field Descriptions
      2. 9.6.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
        1. Table 11. Misc Control 1 Field Descriptions
      3. 9.6.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
        1. Table 12. Misc Control 2 Field Descriptions
      4. 9.6.4  SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
        1. Table 13. SAP Control Field Descriptions
      5. 9.6.5  Channel State Control Register (address = 0x04) [default = 0x55]
        1. Table 14. Channel State Control Field Descriptions
      6. 9.6.6  Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
        1. Table 15. Ch x Volume Control Field Descriptions
      7. 9.6.7  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
        1. Table 16. DC Load Diagnostics Control 1 Field Descriptions
      8. 9.6.8  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
        1. Table 17. DC Load Diagnostics Control 2 Field Descriptions
      9. 9.6.9  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
        1. Table 18. DC Load Diagnostics Control 3 Field Descriptions
      10. 9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
        1. Table 19. DC Load Diagnostics Report 1 Field Descriptions
      11. 9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
        1. Table 20. DC Load Diagnostics Report 2 Field Descriptions
      12. 9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
        1. Table 21. DC Load Diagnostics Report 3 Line Output Field Descriptions
      13. 9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
        1. Table 22. State-Reporting Field Descriptions
      14. 9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
        1. Table 23. Channel Faults Field Descriptions
      15. 9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
        1. Table 24. Global Faults 1 Field Descriptions
      16. 9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
        1. Table 25. Global Faults 2 Field Descriptions
      17. 9.6.17 Warnings Register (address = 0x13) [default = 0x20]
        1. Table 26. Warnings Field Descriptions
      18. 9.6.18 Pin Control Register (address = 0x14) [default = 0x00]
        1. Table 27. Pin Control Field Descriptions
      19. 9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
        1. Table 28. AC Load Diagnostic Control 1 Field Descriptions
      20. 9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
        1. Table 29. AC Load Diagnostic Control 2 Field Descriptions
      21. 9.6.21 AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A) [default = 0x00]
        1. Table 30. Chx AC LDG Impedance Report Field Descriptions
      22. 9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
        1. Table 31. AC LDG Phase High Report Field Descriptions
      23. 9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
        1. Table 32. AC LDG Phase Low Report Field Descriptions
      24. 9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
        1. Table 33. AC LDG STI High Report Field Descriptions
      25. 9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
        1. Table 34. Chx AC LDG STI Low Report Field Descriptions
      26. 9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
        1. Table 35. Misc Control 3 Field Descriptions
      27. 9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
        1. Table 36. Clip Control Field Descriptions
      28. 9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
        1. Table 37. Clip Window Field Descriptions
      29. 9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
        1. Table 38. Clip Warning Field Descriptions
      30. 9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
        1. Table 39. ILIMIT Status Field Descriptions
      31. 9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
        1. Table 40. Misc Control 4 Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 AM-Radio Band Avoidance
      2. 10.1.2 Parallel BTL Operation (PBTL)
      3. 10.1.3 Demodulation Filter Design
      4. 10.1.4 Line Driver Applications
    2. 10.2 Typical Applications
      1. 10.2.1 BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Communication
        3. 10.2.1.3 Detailed Design Procedure
          1. 10.2.1.3.1 Hardware Design
          2. 10.2.1.3.2 Digital Input and the Serial Audio Port
          3. 10.2.1.3.3 Bootstrap Capacitors
          4. 10.2.1.3.4 Output Reconstruction Filter
        4. 10.2.1.4 Application Curves
      2. 10.2.2 PBTL Application
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 Detailed Design Procedure
        2. 10.2.2.2 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Electrical Connection of Thermal pad and Heat Sink
      2. 12.1.2 EMI Considerations
      3. 12.1.3 General Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.5.2 I2C Bus Protocol

The device has a bidirectional serial-control interface that is compatible with the Inter IC (I2C) bus protocol and supports 100 kbps and 400 kbps data transfer rates for random and sequential write and read operations. The TAS6424M-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.

The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. The number of bytes that can be transmitted between start and stop conditions is unlimited. When the last word transfers, the master generates a stop condition to release the bus.

TAS6424M-Q1 td_i2c_sequence_slos870.gifFigure 41. Typical I2C Sequence
TAS6424M-Q1 td_scl-sda_slos870.gifFigure 42. SCL and SDA Timing

Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted using single-byte or multiple-byte data transfers.