SLOS948
February 2019
TAS6424M-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
PCB AREA
4
Revision History
5
Device Options
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Serial Audio Port
9.3.1.1
I2S Mode
9.3.1.2
Left-Justified Timing
9.3.1.3
Right-Justified Timing
9.3.1.4
TDM Mode
9.3.1.5
Supported Clock Rates
9.3.1.6
Audio-Clock Error Handling
9.3.2
High-Pass Filter
9.3.3
Volume Control and Gain
9.3.4
High-Frequency Pulse-Width Modulator (PWM)
9.3.5
Gate Drive
9.3.6
Power FETs
9.3.7
Load Diagnostics
9.3.7.1
DC Load Diagnostics
9.3.7.2
Line Output Diagnostics
9.3.7.3
AC Load Diagnostics
9.3.7.3.1
Impedance Magnitude Measurement
9.3.7.3.2
Impedance Phase Reference Measurement
9.3.7.3.3
Impedance Phase Measurement
9.3.8
Protection and Monitoring
9.3.8.1
Overcurrent Limit (ILIMIT)
9.3.8.2
Overcurrent Shutdown (ISD)
9.3.8.3
DC Detect
9.3.8.4
Clip Detect
9.3.8.5
Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
9.3.8.6
Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
9.3.8.7
Undervoltage (UV) and Power-On-Reset (POR)
9.3.8.8
Overvoltage (OV) and Load Dump
9.3.9
Power Supply
9.3.9.1
Vehicle-Battery Power-Supply Sequence
9.3.9.2
Boosted Power-Supply Sequence
9.3.10
Hardware Control Pins
9.3.10.1
FAULT
9.3.10.2
WARN
9.3.10.3
MUTE
9.3.10.4
STANDBY
9.4
Device Functional Modes
9.4.1
Operating Modes and Faults
9.5
Programming
9.5.1
I2C Serial Communication Bus
9.5.2
I2C Bus Protocol
9.5.3
Random Write
9.5.4
Sequential Write
9.5.5
Random Read
9.5.6
Sequential Read
9.6
Register Maps
9.6.1
Mode Control Register (address = 0x00) [default = 0x00]
Table 10.
Mode Control Field Descriptions
9.6.2
Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
Table 11.
Misc Control 1 Field Descriptions
9.6.3
Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
Table 12.
Misc Control 2 Field Descriptions
9.6.4
SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
Table 13.
SAP Control Field Descriptions
9.6.5
Channel State Control Register (address = 0x04) [default = 0x55]
Table 14.
Channel State Control Field Descriptions
9.6.6
Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
Table 15.
Ch x Volume Control Field Descriptions
9.6.7
DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
Table 16.
DC Load Diagnostics Control 1 Field Descriptions
9.6.8
DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
Table 17.
DC Load Diagnostics Control 2 Field Descriptions
9.6.9
DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
Table 18.
DC Load Diagnostics Control 3 Field Descriptions
9.6.10
DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
Table 19.
DC Load Diagnostics Report 1 Field Descriptions
9.6.11
DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
Table 20.
DC Load Diagnostics Report 2 Field Descriptions
9.6.12
DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
Table 21.
DC Load Diagnostics Report 3 Line Output Field Descriptions
9.6.13
Channel State Reporting Register (address = 0x0F) [default = 0x55]
Table 22.
State-Reporting Field Descriptions
9.6.14
Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
Table 23.
Channel Faults Field Descriptions
9.6.15
Global Faults 1 Register (address = 0x11) [default = 0x00]
Table 24.
Global Faults 1 Field Descriptions
9.6.16
Global Faults 2 Register (address = 0x12) [default = 0x00]
Table 25.
Global Faults 2 Field Descriptions
9.6.17
Warnings Register (address = 0x13) [default = 0x20]
Table 26.
Warnings Field Descriptions
9.6.18
Pin Control Register (address = 0x14) [default = 0x00]
Table 27.
Pin Control Field Descriptions
9.6.19
AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
Table 28.
AC Load Diagnostic Control 1 Field Descriptions
9.6.20
AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
Table 29.
AC Load Diagnostic Control 2 Field Descriptions
9.6.21
AC Load Diagnostic Impedance Report Ch1 through CH4 Registers (address = 0x17–0x1A) [default = 0x00]
Table 30.
Chx AC LDG Impedance Report Field Descriptions
9.6.22
AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
Table 31.
AC LDG Phase High Report Field Descriptions
9.6.23
AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
Table 32.
AC LDG Phase Low Report Field Descriptions
9.6.24
AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
Table 33.
AC LDG STI High Report Field Descriptions
9.6.25
AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
Table 34.
Chx AC LDG STI Low Report Field Descriptions
9.6.26
Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
Table 35.
Misc Control 3 Field Descriptions
9.6.27
Clip Control Register (address = 0x22) [default = 0x01]
Table 36.
Clip Control Field Descriptions
9.6.28
Clip Window Register (address = 0x23) [default = 0x14]
Table 37.
Clip Window Field Descriptions
9.6.29
Clip Warning Register (address = 0x24) [default = 0x00]
Table 38.
Clip Warning Field Descriptions
9.6.30
ILIMIT Status Register (address = 0x25) [default = 0x00]
Table 39.
ILIMIT Status Field Descriptions
9.6.31
Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
Table 40.
Misc Control 4 Field Descriptions
10
Application and Implementation
10.1
Application Information
10.1.1
AM-Radio Band Avoidance
10.1.2
Parallel BTL Operation (PBTL)
10.1.3
Demodulation Filter Design
10.1.4
Line Driver Applications
10.2
Typical Applications
10.2.1
BTL Application
10.2.1.1
Design Requirements
10.2.1.2
Communication
10.2.1.3
Detailed Design Procedure
10.2.1.3.1
Hardware Design
10.2.1.3.2
Digital Input and the Serial Audio Port
10.2.1.3.3
Bootstrap Capacitors
10.2.1.3.4
Output Reconstruction Filter
10.2.1.4
Application Curves
10.2.2
PBTL Application
10.2.2.1
Design Requirements
10.2.2.1.1
Detailed Design Procedure
10.2.2.2
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.1.1
Electrical Connection of Thermal pad and Heat Sink
12.1.2
EMI Considerations
12.1.3
General Guidelines
12.2
Layout Example
12.3
Thermal Considerations
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
Community Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DKQ|56
MPDS378A
Thermal pad, mechanical data (Package|Pins)
DKQ|56
PPTD313D
Orderable Information
slos948_oa
slos948_pm
10.2
Typical Application
s