SLOSE66 november   2020 TAS6424MS-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Audio Port
        1. 9.3.1.1 I2S Mode
        2. 9.3.1.2 Left-Justified Timing
        3. 9.3.1.3 Right-Justified Timing
        4. 9.3.1.4 TDM Mode
        5. 9.3.1.5 Supported Clock Rates
        6. 9.3.1.6 Audio-Clock Error Handling
      2. 9.3.2  High-Pass Filter
      3. 9.3.3  Volume Control and Gain
      4. 9.3.4  High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5  Channel-to-Channel Phase Control
      6. 9.3.6  Gate Drive
      7. 9.3.7  Power FETs
      8. 9.3.8  Load Diagnostics
        1. 9.3.8.1 DC Load Diagnostics
        2. 9.3.8.2 Line Output Diagnostics
        3. 9.3.8.3 AC Load Diagnostics
          1. 9.3.8.3.1 Impedance Magnitude Measurement
          2. 9.3.8.3.2 Impedance Phase Reference Measurement
          3. 9.3.8.3.3 Impedance Phase Measurement
      9. 9.3.9  Protection and Monitoring
        1. 9.3.9.1 Overcurrent Limit (ILIMIT)
        2. 9.3.9.2 Overcurrent Shutdown (ISD)
        3. 9.3.9.3 DC Detect
        4. 9.3.9.4 Clip Detect
        5. 9.3.9.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 9.3.9.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 9.3.9.7 Undervoltage (UV) and Power-On-Reset (POR)
        8. 9.3.9.8 Overvoltage (OV) and Load Dump
      10. 9.3.10 Power Supply
        1. 9.3.10.1 Vehicle-Battery Power-Supply Sequence
        2. 9.3.10.2 Power-Down Sequence
        3. 9.3.10.3 Boosted Power-Supply Sequence
      11. 9.3.11 Hardware Control Pins
        1. 9.3.11.1 FAULT
        2. 9.3.11.2 WARN
        3. 9.3.11.3 MUTE
        4. 9.3.11.4 STANDBY
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes and Faults
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Communication Bus
      2. 9.5.2 I2C Bus Protocol
      3. 9.5.3 Random Write
      4. 9.5.4 Sequential Write
      5. 9.5.5 Random Read
      6. 9.5.6 Sequential Read
    6. 9.6 Register Maps
      1. 9.6.1  Mode Control Register (address = 0x00) [default = 0x00]
      2. 9.6.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 9.6.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 9.6.4  SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
      5. 9.6.5  Channel State Control Register (address = 0x04) [default = 0x55]
      6. 9.6.6  Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
      7. 9.6.7  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      8. 9.6.8  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      9. 9.6.9  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      10. 9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      11. 9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      12. 9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
      13. 9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
      14. 9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
      15. 9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
      16. 9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
      17. 9.6.17 Warnings Register (address = 0x13) [default = 0x20]
      18. 9.6.18 Pin Control Register (address = 0x14) [default = 0x00]
      19. 9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      20. 9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      21. 9.6.21 AC Load Diagnostic Impedance Report Ch1 through Ch4 Registers (address = 0x17–0x1A) [default = 0x00]
      22. 9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
      23. 9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
      24. 9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
      25. 9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
      26. 9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      27. 9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
      28. 9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
      29. 9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
      30. 9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
      31. 9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
      1. 10.1.1 AM-Radio Band Avoidance
      2. 10.1.2 Parallel BTL Operation (PBTL)
      3. 10.1.3 Demodulation Filter Design
      4. 10.1.4 Line Driver Applications
    2. 10.2 Typical Applications
      1. 10.2.1 BTL Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 Communication
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Hardware Design
          2. 10.2.1.2.2 Digital Input and the Serial Audio Port
          3. 10.2.1.2.3 Bootstrap Capacitors
          4. 10.2.1.2.4 Output Reconstruction Filter
      2. 10.2.2 PBTL Application
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Typical Characteristics

TA = 25 °C, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C settings, see Figure 10-2 and Figure 10-3 (unless otherwise noted)

GUID-39094B28-1E25-4A1A-9B31-CCD494BA7339-low.gif
PO = 1 W
Figure 7-1 Crosstalk vs Frequency
GUID-234BD249-7A9A-4BCD-B842-5560296DD0AF-low.gif
PO = 1 W
Figure 7-3 VBAT PSRR vs Frequency
GUID-EB2508C6-B59B-4B39-B9BA-00336BF818BA-low.gif
PO = 1 W fSW = 2.1 MHz
Figure 7-5 THD+N vs Frequency
GUID-F24FA525-CC83-46B3-B191-6ABF75F6A4F6-low.gif
fSW = 2.1 MHz
Figure 7-7 THD+N vs Power
GUID-FFC56A3F-AC88-4610-BCF5-E1233B90E43C-low.gif
10% THD
Figure 7-9 Output Power vs Supply Voltage
GUID-AA6CE3E1-B91F-4023-B46B-80A72F8CD445-low.gif
4 Ω fSW = 384 kHz
Figure 7-11 PVDD Power Efficiency vs Total Output Power
GUID-A88B8D63-D885-495D-88B6-15E9E38DD4CE-low.gif
2 Ω fSW = 384 kHz
Figure 7-13 PVDD Power Efficiency vs Total Output Power
GUID-47CA6A34-D63E-42D9-BF50-583403D7901C-low.gif
Figure 7-15 PVDD Idle Current vs Voltage
GUID-3FEE2B7C-3517-49CD-881C-DE6738925090-low.gif
Figure 7-17 PVDD Standby Current vs Voltage
GUID-24BF8749-82BE-4DBC-98FD-61626A3B00FE-low.gif
PO = 1 W fSW = 2.1 MHz
Figure 7-19 PBTL THD+N vs Frequency
GUID-678FBB6E-3CFB-4E1C-90D8-3C9642B46C96-low.gif
fSW = 2.1 MHz
Figure 7-21 PBTL THD+N vs Power
GUID-82A896B3-A95C-4E17-92BF-F39A17F5B957-low.gif
10 % THD fSW = 2.1 MHz
Figure 7-23 PBTL Output Power vs Voltage
GUID-D1935C31-0187-435B-9DB1-57C422B8679B-low.gif
fSW = 2.1 MHz
Figure 7-25 Power Dissipation vs Total Output Power
GUID-F5E99E6C-2160-4B93-924A-581994227B7A-low.gif
PO = 1 W
Figure 7-2 PVDD PSRR vs Frequency
GUID-A981BE44-EB42-4ACD-A126-8689FD0D6C5D-low.gif
PO = 1 W fSW = 384 kHz
Figure 7-4 THD+N vs Frequency
GUID-E9D119D9-2642-4D02-8224-96294EACF9A7-low.gif
fSW = 384 kHz
Figure 7-6 THD+N vs Power
GUID-E1D4E1D7-80C5-44A0-A45C-66650397F947-low.gif
10% THD fSW = 384 kHz
Figure 7-8 Output Power vs Supply Voltage
GUID-E87F7CAF-D6D5-499F-B94C-7C2CDB402287-low.gif
A-weighted Noise fSW = 2.1 MHz
Figure 7-10 Noise vs Supply voltage
GUID-4343BEE5-221D-4ABD-A351-F3A68BA11A1E-low.gif
4 Ω fSW = 2.1 MHz
Figure 7-12 PVDD Power Efficiency vs Total Output Power
GUID-9323009D-E114-465A-9AF6-1648F630FBBF-low.gif
2 Ω fSW = 2.1 MHz
Figure 7-14 PVDD Power Efficiency vs Total Output Power
GUID-F6720CE5-E9E9-4B0D-9FEB-557E973A3191-low.gif
Figure 7-16 VBAT Idle Current vs Voltage
GUID-340BE286-07E9-4CF1-BEB8-B850E347AA46-low.gif
1 W fSW = 384 kHz
Figure 7-18 PBTL THD+N vs Frequency
GUID-938D3AD8-887A-446D-8255-3E89E3DFDABB-low.gif
fSW = 384 kHz
Figure 7-20 PBTL THD+N vs Power
GUID-8C7F4B84-CFF2-45D5-9D17-A136057027C1-low.gif
10 % THD fSW = 384 kHz
Figure 7-22 PBTL Output Power vs Voltage
GUID-19EA90E7-E239-4EF4-AF49-2A96D722CC6D-low.gif
fSW = 384 kHz
Figure 7-24 Power Dissipation vs Total Output Power