SLOSE66 november   2020 TAS6424MS-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Serial Audio Port
        1. 9.3.1.1 I2S Mode
        2. 9.3.1.2 Left-Justified Timing
        3. 9.3.1.3 Right-Justified Timing
        4. 9.3.1.4 TDM Mode
        5. 9.3.1.5 Supported Clock Rates
        6. 9.3.1.6 Audio-Clock Error Handling
      2. 9.3.2  High-Pass Filter
      3. 9.3.3  Volume Control and Gain
      4. 9.3.4  High-Frequency Pulse-Width Modulator (PWM)
      5. 9.3.5  Channel-to-Channel Phase Control
      6. 9.3.6  Gate Drive
      7. 9.3.7  Power FETs
      8. 9.3.8  Load Diagnostics
        1. 9.3.8.1 DC Load Diagnostics
        2. 9.3.8.2 Line Output Diagnostics
        3. 9.3.8.3 AC Load Diagnostics
          1. 9.3.8.3.1 Impedance Magnitude Measurement
          2. 9.3.8.3.2 Impedance Phase Reference Measurement
          3. 9.3.8.3.3 Impedance Phase Measurement
      9. 9.3.9  Protection and Monitoring
        1. 9.3.9.1 Overcurrent Limit (ILIMIT)
        2. 9.3.9.2 Overcurrent Shutdown (ISD)
        3. 9.3.9.3 DC Detect
        4. 9.3.9.4 Clip Detect
        5. 9.3.9.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
        6. 9.3.9.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
        7. 9.3.9.7 Undervoltage (UV) and Power-On-Reset (POR)
        8. 9.3.9.8 Overvoltage (OV) and Load Dump
      10. 9.3.10 Power Supply
        1. 9.3.10.1 Vehicle-Battery Power-Supply Sequence
        2. 9.3.10.2 Power-Down Sequence
        3. 9.3.10.3 Boosted Power-Supply Sequence
      11. 9.3.11 Hardware Control Pins
        1. 9.3.11.1 FAULT
        2. 9.3.11.2 WARN
        3. 9.3.11.3 MUTE
        4. 9.3.11.4 STANDBY
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes and Faults
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Communication Bus
      2. 9.5.2 I2C Bus Protocol
      3. 9.5.3 Random Write
      4. 9.5.4 Sequential Write
      5. 9.5.5 Random Read
      6. 9.5.6 Sequential Read
    6. 9.6 Register Maps
      1. 9.6.1  Mode Control Register (address = 0x00) [default = 0x00]
      2. 9.6.2  Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
      3. 9.6.3  Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
      4. 9.6.4  SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
      5. 9.6.5  Channel State Control Register (address = 0x04) [default = 0x55]
      6. 9.6.6  Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF]
      7. 9.6.7  DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
      8. 9.6.8  DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
      9. 9.6.9  DC Load Diagnostic Control 3 Register (address = 0x0B) [default = 0x11]
      10. 9.6.10 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
      11. 9.6.11 DC Load Diagnostic Report 2 Register (address = 0x0D) [default = 0x00]
      12. 9.6.12 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
      13. 9.6.13 Channel State Reporting Register (address = 0x0F) [default = 0x55]
      14. 9.6.14 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
      15. 9.6.15 Global Faults 1 Register (address = 0x11) [default = 0x00]
      16. 9.6.16 Global Faults 2 Register (address = 0x12) [default = 0x00]
      17. 9.6.17 Warnings Register (address = 0x13) [default = 0x20]
      18. 9.6.18 Pin Control Register (address = 0x14) [default = 0x00]
      19. 9.6.19 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
      20. 9.6.20 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
      21. 9.6.21 AC Load Diagnostic Impedance Report Ch1 through Ch4 Registers (address = 0x17–0x1A) [default = 0x00]
      22. 9.6.22 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
      23. 9.6.23 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
      24. 9.6.24 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
      25. 9.6.25 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
      26. 9.6.26 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
      27. 9.6.27 Clip Control Register (address = 0x22) [default = 0x01]
      28. 9.6.28 Clip Window Register (address = 0x23) [default = 0x14]
      29. 9.6.29 Clip Warning Register (address = 0x24) [default = 0x00]
      30. 9.6.30 ILIMIT Status Register (address = 0x25) [default = 0x00]
      31. 9.6.31 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
      1. 10.1.1 AM-Radio Band Avoidance
      2. 10.1.2 Parallel BTL Operation (PBTL)
      3. 10.1.3 Demodulation Filter Design
      4. 10.1.4 Line Driver Applications
    2. 10.2 Typical Applications
      1. 10.2.1 BTL Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 Communication
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Hardware Design
          2. 10.2.1.2.2 Digital Input and the Serial Audio Port
          3. 10.2.1.2.3 Bootstrap Capacitors
          4. 10.2.1.2.4 Output Reconstruction Filter
      2. 10.2.2 PBTL Application
        1. 10.2.2.1 Design Requirements
          1. 10.2.2.1.1 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, f = 1kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
IPVDD_IDLE PVDD idle current All channels playing, no audio input 75 90 mA
IVBAT_IDLE VBAT idle current All channels playing, no audio input 90 100 mA
IPVDD_STBY PVDD standby current STANDBY Active, VDD = 0 V 0.5 1 µA
IVBAT_STBY VBAT standby current STANDBY Active, VDD = 0 V 4 6 µA
IVDD VDD supply current All channels playing, –60-dB signal 15 18 mA
OUTPUT POWER
PO_BTL Output power per channel, BTL 4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 20 22 W
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 25 27
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 38 40
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 42 45
4 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C 30 33
4 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C 40 45
PO_PBTL Output power per channel in parallel mode, PBTL 2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 35 40 W
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 45 50
1 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C 72 80
1 Ω, PVDD = 14.4 V, THD+N = 10%, TC = 75°C 80 90
2 Ω, PVDD = 18 V, THD+N = 1%, TC = 75°C 60 65
2 Ω, PVDD = 18 V, THD+N = 10%, TC = 75°C 75 80
EFFP Power efficiency 4 channels operating, 25-W output power/ch 4 Ω load,PVDD = 14.4 V, TC = 25°C 86%
AUDIO PERFORMANCE
Vn Output noise voltage Zero input, A-weighting, gain level 1, PVDD = 14.4 V 42 µV
Zero input, A-weighting, gain level 2, PVDD = 14.4 V 55
Zero input, A-weighting, gain level 3, PVDD = 18 V 67
Zero input, A-weighting, gain level 4, PVDD = 18 V 85
GAIN Peak Output Voltage/dBFS gain level 1, Register 0x01, bit 1-0 = 00 7.5 V/FS
gain level 2, Register 0x01, bit 1-0 = 01 15
gain level 3, Register 0x01, bit 1-0 = 10 21
gain level 4, Register 0x01, bit 1-0 = 11 29
GAINVAR Channel Gain Variation Gain variation for all gain levels. -0.5 0.5 dB
Crosstalk Channel crosstalk PVDD = 14.4 Vdc + 1 VRMS, f = 1 kHz -90 dB
PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, f = 1 kHz 75 dB
THD+N Total harmonic distortion + noise 0.02
GCH Channel-to-channel gain variation -0.5 0 0.5 dB
LINE OUTPUT PERFROMANCE
Vn_LINEOUT LINE output noise voltage Zero input, A-weighting, channel set to LINE MODE 42 µV
VO_LINEOUT LINE output voltage 0dB input, channel set to LINE MODE 5.5 VRMS
THD+N Line output total harmonic distortion + noise VO = 2 VRMS , channel set to LINE MODE 0.01
DIGITAL INPUT PINS
VIH Input logic level high 70 %VDD
VIL Input logic level low 30 %VDD
IIH Input logic current, high VI = VDD 15 µA
IIL Input logic current, low VI = 0 -15 µA
PWM OUTPUT STAGE
RDS(on) FET drain-to-source resistance Not including bond wire and package resistance 90 mΩ
OVER VOLTAGE (OV) PROTECTIONI
VPVDD_OV PVDD overvoltage shutdown 19.3 20 22 V
VPVDD_OV_HY S PVDD overvoltage shutdown hysteresis 0.8 V
VVBAT_OV VBAT overvoltage shutdown 20 21.5 23 V
VVBAT_OV_HY S VBAT overvoltage shutdown hysteresis 0.6
UNDER VOLTAGE (UV) PROTECTIONI
VBATUV VBAT undervoltage shutdown 4 4.5 V
VBATUV_HYS VBAT undervoltage shutdown hysteresis 0.2 V
PVDDUV PVDD undervoltage shutdown 4 4.5 V
PVDDUV_HY S PVDD undervoltage shutdown hysteresis 0.2 V
BYPASS VOLTAGES
VGVDD Gate drive bypass pin voltage 7 V
VAVDD Analog bypass pin voltage 6 V
VVCOM Common bypass pin voltage 2.5 V
VVREG Regulator bypass pin voltage 5.5 V
POWER-ON RESET(POR)
VPOR VDD voltage for POR 2.1 2.7 V
VPOR_HY VDD POR recovery hysteresis voltage 0.5 V
OVER TEMPERATURE (OT) PROTECTION
OTW(i) Channel overtemperature warning 150 °C
OTSD(i) Channel overtemperature shutdown 175 °C
OTW Global junction overtemperature warning 130 °C
OTSD Global junction overtemperature shutdown 160 °C
OTHYS Overtemperature hysteresis 15 °C
LOAD OVER CURRENT PROTECTION
ILIM Overcurrent cycle-by-cycle limit OC Level 1 4.0 4.8 A
OC Level 2 6.0 7 A
ISD Overcurrent shutdown OC Level 1, Any short to supply, ground, or other channels 7 A
OC Level 2, Any short to supply, ground, or other channels 9 A
MUTE MODE
GMUTE Output attenuation 100 dB
CLICK AND POP
VCP Output click and pop voltage ITU-R 2k filter, High-Z/MUTE to Play, Play to Mute/High-Z 7 mV
DC OFFSET
VOFFSET Output offset voltage 2 5 mV
DC DETECT
DCFAULT Output DC fault protection 2 2.5 V
DIGITAL OUTPUT PINS
VOH Output voltage for logic level high I = ±2 mA 90 %VDD
VOL Output voltage for logic level low I = ±2 mA 10 %VDD
tDELAY_CLIPDE T Signal delay when output clipping detected 20 µs
LOAD DIAGNOSTICS
S2P Maximum resistance to detect a short from OUT pin(s) to PVDD 500 Ω
S2G Maximum resistance to detect a short from OUT pin(s) to ground 200 Ω
SL Shorted load detection tolerance Other channels in Hi-Z ±0.5 Ω
OL Open load Other channels in Hi-Z 40 70 Ω
TDC_DIAG DC diagnostic time All 4 Channels 230 ms
LO Line output 6 kΩ
TLINE_DIAG Line output diagnostic time 40 ms
ACIMP AC impedance accuracy Offset ±0.5 Ω
Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω 0.25
TAC_DIAG AC diagnostic time All 4 Channels 520 ms
I2C_ADDR PINS
tI2C_ADDR Time delay needed for I2C address set-up 300 µs
I2C CONTROL PORT
tBUS Bus free time between start and stop conditions 1.3 µs
tHOLD1 Hold time, SCL to SDA 0 ns
tHOLD2 Hold time, start condition to SCL 0.6 µs
tSTART I2C startup time after VDD power on reset 12 ms
tRISE Rise time, SCL and SDA 300 ns
tFALL Fall time, SCL and SDA 300 ns
tSU1 Setup, SDA to SCL 100 ns
tSU2 Setup, SCL to start condition 0.6 µs
tSU3 Setup, SCL to stop condition 0.6 µs
tW(H) Required pulse duration SCL high 0.6 µs
tW(L) Required pulse duration SCL low 1.3 µs
SERIAL AUDIO PORT
DMCLK, DSCLK Allowable input clock duty cycle 0.45 0.5 0.55
fMCLK Supported MCLK frequencies 128, 256, or 512 128 512 xFS
fMCLK_Max Maximum frequency 25 MHz
tSCY SCLK pulse cycle time 40 ns
tSCL SCLK pulse-with LOW 16 ns
tSCH SCLK pulse-with HIGH 16 ns
tRISE/FALL Rise and fall time <5 ns
tSF Required FSYNC to SCLK rising edge 8 ns
tFS FSYNC rising edge to SCLK edge 8 ns
tDS DATA set-up time 8 ns
tDH DATA hold time 8 ns
th Required SDIN hold time after SCLK rising edge 15 ns
tsu Required SDIN setup time before SCLK rising edge 15 ns
Ci Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1, SDIN2 10 pf
TLA Latency from input to output measured in FSYNC sample count FSYNC = 44.1 kHz or 48 kHz 30
FSYNC = 96 kHz 12