SCPS274B June 2021 – March 2023 TCA39306
PRODUCTION DATA
The maximum frequency of the device depends on the application. The device can operate at speeds of > 100 MHz given the correct conditions. The maximum frequency is dependent upon the loading of the application.
However, this is an analog type of measurement. For digital applications, the signal should not degrade up to the fifth harmonic of the digital signal. The frequency bandwidth should be at least five times the maximum digital clock rate. This component of the signal is important in determining the overall shape of the digital signal. In the case of the device, digital clock frequency of >100 MHz can be achieved.
The device does not provide any drive capability like the TCA9517 or other buffered translators. Therefore, higher-frequency applications require higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the device is being driven by standard CMOS push-pull output driver. Ideally, it is best to minimize the trace length from device on the sink side (1.8 V) to minimize signal degradation.
You can then use a simple formula to compute the maximum practical frequency component or the knee frequency (fknee). All fast edges have an infinite spectrum of frequency components. However, there is an inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than fknee are insignificant in determining the shape of the signal.
To calculate fknee:
For signals with rise-time characteristics based on 10- to 90-percent thresholds, fknee is equal to 0.5 divided by the rise time of the signal. For signals with rise-time characteristics based on 20- to 80-percent thresholds, which is very common in many current device specifications, fknee is equal to 0.4 divided by the rise time of the signal.
Some guidelines to follow that help maximize the performance of the device: