8.4.7.1 CLK Switching

The CLK output on each of the smartcard interfaces can be controlled by the corresponding clock settings register (Reg 0x02 for user card, Reg 0x12 for SAM1, Reg 0x22 for SAM2, Reg 0x32 for SAM3). The CLKIN1 pin is dedicated for the user card interface while The CLKIN2 is shared between the SAM interfaces. The clock settings register allows the CLK output to be configured in one of 4 different modes.

1. CLK 0 mode - The CLK output of the card interface is static low.
2. CLK 1 mode - The CLK output of the card interface is static high.
3. CLK div mode - The CLK output is a divided down frequency of the CLKIN1 or CLKIN2 frequency. Bit [4:2] of clock settings register defines the division ratio.
4. Internal CLK mode - The CLK output is at a fixed frequency (~1.2 MHz) based off the internal oscillator.

The allowable changes in CLK output can vary depending on the mode in which the interface has been activated. In asynchronous mode (see Asynchronous Operating Mode), The CLK output can be dynamically switched from one state to another. Table 8 shows the permitted frequency transitions on CLK pin in asynchronous mode. Any I²C command that attempts to switch the CLK frequency outside of these state transitions can result in the change not happening on the output or other unpredictable behavior that could cause device to lock up. If the device enters such a locked state, it can be reset by toggling SHDN pin.

When command sets the device in Internal clock mode or CLK 0 mode or CLK 1 mode, the division ratio is locked out, that is, when an I²C transaction that sets either one of the bits [7:5] of the card clock settings register to 1, the remaining bits in the register (bit [4:2]) will not not be updated. It is to be noted that an asynchronous activation cannot be performed with the internal clock. At the start of the asynchronous activation, if the internal CLK mode is selected in the clock settings register, then the device shall begin activation based on divide ratio defined by bit [4:2] of clock settings register. After the activation is completed, the CLK output will switch to Internal CLK mode. When switching to/from a CLK div mode from/to CLK 0 mode or CLK 1 mode, the device waits for the input clock (CLKIN1 or CLKIN2) phase to match the static level it will switch to/from and then makes the transition to ensure that no partial pulses or glitches are seen on the output clock. Similarly, when switching from one division ratio to another the change happens on the rising clock edges to ensure no glitch on the output. Figure 15 shows how the change in divide ratio is seen on the CLK pin.

Figure 15. CLK Divide Ratio Change on Card CLK Output

When switching from CLK divide mode to the Internal CLK mode, the device waits for the edges of the internal and external clock to line up (fall within ~10 ns of each other) and makes the switch on that edge. If the external clock is close to an exact harmonic of 1.2 MHz, there could be a situation where the rising edges of the two clocks take very long (milliseconds or seconds) to line up and this would mean the frequency switch at the output would happen long after the I²C command to make the switch is issued. The CLKSW bit (bit [3]) in the card interface status register (Reg 0x01 for user card, Reg 0x11 for SAM1, Reg 0x21 for SAM2, Reg 0x31for SAM3) is set when the internal clock frequency is seen on the CLK pin.

Figure 16. Output CLK Frequency Transition When Switching From External Clock to Internal Clock

In CLK divide mode, when CLKIN/2, CLKIN/4 or CLKIN/8 division ratios are used, the output duty cycle is not affected by the duty cycle of the input clock on CLKIN. When the CLKIN/1 and CLKIN/5 division ratios are used, the output clock duty cycle is a function of the CLKIN1/CLKIN2 duty cycle. For CLKIN/1 the output duty cycle will be equal to the input duty cycle. For CLKIN/5 the output CLK duty cycle is given by (n+2) / 5, where n is the duty cycle of the input clk; for example, if the input clk has a 40% duty cycle (n = 0.4) the CLKIN/5 output will have a (0.4+2) / 5 = 0.48 or 48% duty cycle. In addition to asynchronous mode, the user card interface can also operate in synchronous mode (see Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode).When in synchronous mode the user card CLK pin output is controlled by CLK_ENABLE_SYNC (bit [2], Reg 0x09) in addition to the clock settings register. Figure 17 shows a simplified logical representation of the user card clock muxing circuit.

Figure 17. Clock Muxing Logic in Synchronous Mode

Unlike all the other bits that control the CLK, the CLK_ENABLE_SYNC can cause the CLK state to transition instantly. This means that when switching from a static level to a toggling CLK (or vice-versa), there can be partial pulses (glitches) on the CLK output when CLK_ENABLE_SYNC is switched. In sync mode, the CLK output can be switched directly from one static level to another, by using the CLK settings register (when CLK_SYNC_ENABLE = 0).