SCPS193D July   2010  – January 2023 TCA6424A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (continued)
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Translation
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 I2C Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Address
    5. 8.5 Programming
      1. 8.5.1 Power-On Reset
      2. 8.5.2 Reset Input ( RESET)
      3. 8.5.3 Interrupt Output ( INT)
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Writes
        2. 8.5.4.2 Reads
    6. 8.6 Register Maps
      1. 8.6.1 Control Register and Command Byte
      2. 8.6.2 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Detailed Design Procedure
        1. 9.1.1.1 Minimizing ICC When I/Os Control LEDs
    2. 9.2 Power Supply Recommendation
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.