8.3.1 Seven LED Driver Outputs

The TCA6507 features 7 outputs that can be controlled with multiple modes: ON, OFF, blinking (one of the two separate banks), and fading at a programmable rate (one of the two separate banks).

8.3.2 Open-Drain Outputs Directly Drive LEDs

The TCA6507 has open-drain outputs (see Figure 11) that are capable of sinking current up to 40 mA for LEDs.

8.3.3 Widely Programmable

The TCA6507 has two separate banks, which can be programmed to do a wide variety of blink rates, fade-ON and fade-OFF rates, as well as maximum intensity (brightness).

8.4.1 Power-On Reset

When power (from 0 V) is applied to V_CC, an internal power-on reset holds the TCA6507 in a reset condition until V_CC has reached V_POR. At that point, the reset condition is released, and the TCA6507 registers and I²C/SMBus state machine initialize to their default states.

After the initial power-up phase, V_CC must be lowered to below 0.2 V, and then back up to the operating voltage (V_CC) for a power-reset cycle.

8.4.2 Enable and Reset

If the enable (EN) input is set to low, the TCA6507 is put in the standby or shutdown mode. In this mode, the oscillator is turned off, the registers are returned to their default state, and the I²C/SMBus state machine is initialized. This mode is useful for low-power consumption. An internal filtering circuit prevents negative glitches from accidentally shutting down the device. EN must be low for a minimum of approximately 60 μs to ensure a shutdown state.

The system master can reset the TCA6507 in the event of a timeout or other improper operation by setting
EN low for a minimum of approximately 60 μs. This has the same effect as a power-on reset without powering-down the TCA6507.

The oscillator start up time (t_OSC) is measured from the point when EN is set high.

8.5.1 I²C Interface

The TCA6507 has a standard bidirectional I²C interface that is controlled by a master device to be configured or read the status of this device. Each slave on the I²C bus has a specific device address to differentiate between other slave devices that are on the same I²C bus. Many slave devices require configuration upon startup to set the behavior of the device. This is typically done when the master accesses internal register maps of the slave, which have unique register addresses. A device can have one, or multiple registers where data is stored, written, or read.

The physical I²C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to V_CC through a pullup resistor. The size of the pullup resistor is determined by the amount of capacitance on the I²C lines. For further details, see the I²C Pullup Resistor Calculation application report. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition.

Figure 12 and Figure 13 show the general procedure for a master to access a slave device:

1. If a master wants to send data to a slave:
   • Master-transmitter sends a START condition and addresses the slave-receiver
   • Master-transmitter sends data to slave-receiver
   • Master-transmitter terminates the transfer with a STOP condition
2. If a master wants to receive or read data from a slave:
   • Master-receiver sends a START condition and addresses the slave-transmitter
   • Master-receiver sends the requested register to read to slave-transmitter
   • Master-receiver receives data from the slave-transmitter
   • Master-receiver terminates the transfer with a STOP condition

Figure 12. Definition of START and STOP Conditions

Figure 13. Bit Transfer

8.5.2 Bus Transactions

Data must be sent to and received from the slave devices, and this is accomplished by reading from or writing to registers in the slave device.

Registers are locations in the memory of the slave that contain information, whether it be the configuration information, or some sampled data to send back to the master. The master must write information to these registers to instruct the slave device to perform a task.

8.5.2.1 Writes

To write on the I²C bus, the master sends a START condition on the bus with the address of the slave, as well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting the master know it is ready. After this, the master starts sending the register data to the slave until the master has sent all the data necessary (which can be only a single byte), and the master terminates the transmission with a STOP condition.

Figure 14 shows an example of writing a single byte to a register.

Figure 14. Write to Register

Figure 15 shows an example of writing to a Fully On register.

Figure 15. Write to the Fully On Register (0x04)

8.5.2.2 Reads

Reading from a slave is very similar to writing, but requires some additional steps. To read from a slave, the master must first instruct the slave which register it wishes to read from. This is done by the master starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. Once the slave acknowledges this register address, the master sends a START condition again, followed by the slave address with the R/W bit set to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA bus, but continues supplying the clock to the slave. During this part of the transaction, the master becomes the master-receiver, and the slave becomes the slave-transmitter.

The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data. At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for more data. Once the master has received the number of bytes it is expecting, it sends a NACK, signaling to the slave to halt communications and release the bus. The master follows this up with a STOP condition.

Figure 16 shows an example of reading a single byte from a slave register.

Figure 16. Read From Register Example

8.5.3 Device Address

The address of the TCA6507 is shown in Figure 17.

Figure 17. TCA6507 Address

The last bit of the slave address defines the operation (read or write) to be performed. High (1) selects a read operation, and low (0) selects a write operation. Table 2 shows the TCA6507 interface definition.

8.5.4 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is stored in the control register. The last four bits (B0, B1, B2 and B3) of this command byte determine the internal registers (Select0, Select1, Select2, Fade-ON Time, Fully-ON Time, Fade-OFF Time, First Fully-OFF Time, Second Fully-OFF Time, Maximum Intensity and Initialization) that are affected. The command byte is sent only during a write transmission.

After the command byte is received, the I²C master starts sending data bytes. The first data byte goes into the internal register defined by the command byte. Bit B4 in the command byte is used to determine the programming mode. If B4 is low, all data bytes are written to the register defined by B0, B1, B2, and B3. If B4 is high, the last four bits of the command byte are automatically incremented after the byte is written, and the next data byte is stored in the corresponding register. Registers are written in the sequence shown in Table 6. Once the Initialization register (register 0×0A) is written to, the command byte returns to 0 (Select0 register).

The upper three bits (B7–B5) of the command byte must be programmed as zeroes for proper operation.

If a STOP condition occurs after the command byte is received, the TCA6507 stores the command byte and then remains idle until the I²C master sends the next operation.

Figure 18 shows the TCA6507control register bits.

Figure 18. Control Register Bits

Table 3 shows the TCA6507 command byte.

8.5.5 Auto-Increment Mode

In auto-increment mode, the last four bits of the command byte are automatically incremented after the byte is written, and the next data byte is stored in the corresponding register. See Figure 19.

Figure 19.

The registers are written to in the order shown in Table 6.

8.5.6 LED Operation

For LED states, see Figure 10 and Table 8.

It is the combination of Select2, Select1, and Select0 registers that gives the state of the LED or Px.

Bit 0 from the Select0 register, bit = 0 from Select1 register, and bit = 0 from the Select2 register provide the state for P0, or the first LED. Similarly, bit = 1 from the Select0 register, bit 1 from Select1 register, and bit = 1 from the Select2 register provide the state for P1, or the second LED (see Table 4).

8.5.7 Blinking Pattern Control

The Fade-ON time, Fully-ON time, Fade-OFF time, First Fully-OFF time, and Second Fully-OFF time registers must be written to for basic blink control. Each of these registers has eight bits – top four bits for BANK1 (or PWM1), and bottom four bits for BANK0 (or PWM0) (see Table 20).

Each BANK or PWM has a default value of 4 (4b0100), which translates to a time of 256 ms. The largest value for each BANK or PWM is 15 (4b1111), which translates to a time of 16320 ms (see Figure 20 and Table 5).

Figure 20. LED Pattern Sections Per Bank

Figure 21 and Figure 22 show the output port intensity vs LED intensity.

Figure 21. Output Port Voltage vs LED Intensity, Maximum Intensity = 100%

Figure 22. Output Port Voltage vs LED Intensity, Maximum Intensity = 50%

8.5.8 Intensity Control

The Maximum Intensity registers must be written to for setting the intensity of the LED. This register has eight bits – top four bits for BANK1 (or PWM1), and bottom four bits for BANK0 (or PWM0). This register can be written to after sending data to the Second Fully-OFF Time register (see Table 20).

The Maximum Intensity register has a default value of 15 (1111), which translates to 100% brightness
(see Figure 20 and Table 5).

Table 6. Control Register Description

Table 7. Time Parameters

8.6.1 Registers 0x00 - 0x02 (Select Registers)

Table 8 show the Select2, Select1, and Select0 Register States.

Table 9 show the Register 0x00 (Select0 Register).

Table 10 show the Register 0x01 (Select1 Register).

Table 11 show the Register 0x02 (Select2 Register).

To use a P port as a general-purpose output, Select1 and Select0 registers must be set low (or 0), and then the inverse of the data written to the Select2 bit appears on the open-drain output.

The intensity of each bank of LEDs can be customized by programming six registers: Fade-ON Time, Fully-ON Time, Fade-OFF Time, First Fully-OFF Time, Second Fully-OFF Time, and Maximum Intensity registers. Each bank is designed to produce two identical intensity pulses per blink cycle. Both pulses have the same fade-ON, fully-ON and fade-OFF times, but independent fully-OFF times to achieve a double-blink effect when desired.

8.6.2 Register 0x03 (Fade-ON Time)

Table 12 shows the Fade-ON Time Register (Register 0x03).

The Fade-ON Time register (register 0x03) defines the time from the fully-OFF state to the fully-ON state for the LED per region A in Figure 20. The first four bits (C7–C4) in this register set the fade-ON time for BANK1, and the next four bits (C3–C0) set the fade-ON time for BANK0. The data for each bank is a binary number between 0 and 15. For BANK1, the MSB is bit C7, while the least significant bit (LSB) is bit C4. For BANK0, the MSB is bit C3 while the LSB is bit C0. See Table 7 for more information.

8.6.3 Register 0x04 (Fully-ON Time)

Table 13 shows the Fully-ON Time Register (Register 0x04).

The Fully-ON Time register (register 4) defines the time spent at maximum intensity between the fade-ON state and fade-OFF state for the LED per region B in Figure 20. The first four bits (C7–C4) in this register set the
fully-ON time for BANK1, and the next four bits (C3–C0) set the fully-ON time for BANK0. The data for each bank is a binary number between 0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the most significant bit (MSB) is bit C3, while the LSB is bit C0.

See Table 7 for more information on the possible time values.

8.6.4 Register 0x05 (Fade-OFF Time)

Table 14 shows the Fade-OFF Time Register (Register 0x05).

The Fade-OFF Time register (register 5) defines the time from the fully-ON state to the fully-OFF state for the LED per region C in Figure 20. The first four bits (C7–C4) in this register set the fade-OFF time for BANK1, and the next four bits (C3–C0) set the fade-OFF time for BANK0. The data for each bank is a binary number between 0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the MSB is bit C3, while the least significant bit (LSB) is bit C0.

See Table 7 for more information on the possible time values.

8.6.5 Register 0x06 - 0x07 (Fully-OFF Time)

Table 15 and Table 16 show the Fully-OFF Time register (Register 0x06 - 0x07).

The first and second Fully-OFF Time registers (registers 6 and 7) define the time spent at zero intensity (in the fully-OFF state of the LED) per region D and E, respectively, in Figure 20. The first four bits (C7–C4) in this register set the fully-OFF time for BANK1, and the next four bits (C3–C0) set the fully-OFF time for BANK0. The data for each bank is a binary number between 0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the MSB is bit C3, while the LSB is bit C0.

See Table 7 for more information on the possible time values.

8.6.6 Register 0x08 (Maximum Intensity per Bank)

Table 17 shows the Maximum Intensity Register (Register 0x08).

The Maximum Intensity register defines the duty cycle of the waveform driving the LED in its fully-ON state per region F in Figure 20. The first four bits (C7–C4) in this register set the duty cycle for BANK1 and the next four bits (C3–C0) set the duty cycle for BANK0. The data for each bank is a binary number between 0 and 15. For BANK1, the MSB is bit C7, while the LSB is bit C4. For BANK0, the MSB is bit C3, while the LSB is bit C0. The values in this register also define the LED intensity indicated by the BRIGHT_F0 or BRIGHT_F1 modes. The intensity of each LED is updated 125 times per second (every 8 ms with a 32-kHz clock).

The values for each value are shown in Table 18.

8.6.7 Register 0x09 (One-Shot / Master Intensity)

The One-Shot / Master Intensity register (register 9) is an 8-bit register with three functions.

Bits 0–3 set the master intensity value (ALD). It is a binary number between 0 and 15.

Bits 4–5 determine whether the maximum intensity of PWM0 and PWM1 is set by the programmed F value (BRIGHT_F0 or BRIGHT_F1) or the master ALD value. The default value for these bits is 0. Bit 4 supports PWM0 and bit 5 is for PWM1. If bit 4 (or bit 5) is 0, the maximum intensity value for PWM0 (or PWM1) is set by the F value. If bit 4 (or bit 5) is 1, the maximum intensity value for PWM0 (or PWM1) is set by the master ALD value. This allows the user to vary the brightness of all LEDs by changing a single register.

Bits 6–7 determine whether each PWM operates in normal or one-shot mode. Bit 6 supports PWM0 and bit 7 is for PWM1. If bit 6 (or bit 7) is 0, PWM0 (or PWM1) operates in the normal mode where the LEDs goes through the full intensity cycle defined by Table 5 and Figure 20. If bit 6 (or bit 7) is 1, PWM0 (or PWM1) operate in the one-shot mode. In this mode, the LEDs can be used to create a single-shot lighting effect where the LED intensity is valid for a particular segment of the cycle shown in Table 5 and Figure 20. As a note for users who plan to use one-shot mode, the time register corresponding to the sections for the desired one-shot starting location, and immediately after must both have non-zero values in the registers for time in order for one-shot to function as expected.

Table 19 shows the One-Shot / Master Intensity Register.

8.6.8 Register 0x0A (Initialization Register)

The Initialization register (register 0x0A) determines whether to initialize each PWM and, if so, provides the starting point of the LED intensity cycle for each bank. Bits 0–3 (C0–C3) are for BANK0 and bits 4–7 (C4–C7) are for BANK1. Table 20 shws the Initialization Register (Register 0x0A).

Bits 0–2 provide the starting point for PWM0. If bit 3 is high (or 1), it initializes PWM0.

Bits 4–6 provide the starting point for PWM1. If bit 7 is high (or 1), it initialized PWM1.

In the one-shot mode for BANK0, the LEDs start at the beginning of the region defined by C2, C1, and C0 in the Initialization register and, when it reaches the end of that region, the LED stays at that intensity level defined at the end of the region. When the stop point is reached, all P ports attached to PWM0 disconnect from PWM0, and stay at either the maximum intensity level for PWM0 (BRIGHT_F0 or ALD value), or the OFF state. The bits in the Select2 and Select1 registers change to reflect the final state of the LED at that time. PWM0 continues running, and is free to be used by other LEDs. The one-shot mode works similarly for BANK1.

Upon writing to this register, each bank is initialized to the state listed in Table 21 and Table 22.