SCPS238A February   2021  – August 2021 TCA9416

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Architecture
      2. 8.3.2 Enable and Disable
      3. 8.3.3 Pull up resistors on I/O Lines
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Startup Considerations with Large Capacitive Load Mismatches
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 2-bit bidirectional translator for SDA and SCL lines in I2C applications
  • Provides bidirectional voltage translation with no direction pin
  • High-impedance output SCL_A, SDA_A, SCL_B, SDA_B pins when OE = 0 V or VCC = 0 V
  • Internal 10-kΩ pull-up resistor on all SDA and SCL pins are enabled based on respective VCC voltage
  • 1.08 V to 3.6 V on both A and B ports
  • VCC Isolation feature: If either VCC input is at GND, both ports are in the high-impedance state (excluding pull-ups)
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Low Ioff of 2.5 µA when either VCCA or VCCB = 0 V
  • OE input can be tied directly to VCCA or controlled by GPIO
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD Protection exceeds JESD 22
    • 2500-V Human-body model (A114-B)
    • 1500-V Charged-device model (C101)