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  • TCA9538 Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output, Reset, and Configuration Registers

    • SCPS199D August   2014  – October 2016 TCA9538

      PRODUCTION DATA.  

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  • TCA9538 Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output, Reset, and Configuration Registers
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 RESET Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 Interrupt Output (INT)
      3. 8.3.3 RESET Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Map
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
        1. 8.6.3.1 Bus Transactions
          1. 8.6.3.1.1 Writes
          2. 8.6.3.1.2 Reads
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Minimizing ICC When I/Os Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • PW|16
    • MPDS361A
  • DB|16
    • MPDS507A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • scps199d_oa
  • scps199d_pm
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DATA SHEET

TCA9538 Low Voltage 8-Bit I2C and SMBus Low-Power I/O Expander with Interrupt Output, Reset, and Configuration Registers

1 Features

  • Low Standby Current Consumption
  • I2C to Parallel Port Expander
  • Open-Drain Active-Low Interrupt Output
  • Active-Low Reset Input
  • Operating Power-Supply Voltage Range of 1.65 V to 5.5 V
  • 5-V Tolerant I/O Ports
  • 400-kHz Fast I2C Bus
  • Two Hardware Address Pins Allow up to Four Devices on the I2C/SMBus
  • Input and Output Configuration Register
  • Polarity Inversion Register
  • Power-Up With All Channels Configured as Inputs
  • No Glitch on Power Up
  • Noise Filter on SCL/SDA Inputs
  • Latched Outputs With High-Current Drive Maximum Capability for Directly Driving LEDs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

2 Applications

  • Servers
  • Routers (Telecom Switching Equipment)
  • Personal Computers
  • Personal Electronics (example: Gaming Consoles)
  • Industrial Automation
  • Products With GPIO-Limited Processors

3 Description

The TCA9538 is a 16-pin device that provides 8 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I2C bus (or SMBus) protocol. The device can operate with a power supply voltage ranging from 1.65 V to 5.5 V. The device supports both 100-kHz (Standard-mode) and 400-kHz (Fast-mode) clock frequencies. I/O expanders such as the TCA9538 provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, etc.

The features of the TCA9538 include an interrupt that is generated on the INT pin whenever an input port changes state. The A0 and A1 hardware selectable address pins allow up to four TCA9538 devices on the same I2C bus. The device can also be reset to its default sate by using the RESET feature or by cycling the power supply and causing a power-on reset.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TCA9538 TSSOP (16) 5.00 mm × 4.40 mm
SSOP (16) 6.20 mm × 5.30 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Block Diagram

TCA9538 simp_sch_scps199.gif

4 Revision History

Changes from C Revision (October 2015) to D Revision

  • Updated Figure 18 Go

Changes from B Revision (September 2015) to C Revision

  • Added "Time to reset; VCC = 1.65 V-2.3 V" parameter to RESET Timing Requirements table.Go
  • Added "Output data valid; VCC = 1.65 V-2.3 V" to Switching Characteristics table.Go
  • Updated VCC_GW parameter. Go

Changes from A Revision (September 2014) to B Revision

  • Added DB package to datasheet. Go

Changes from * Revision (August 2014) to A Revision

  • Updated document to full version. Go

5 Pin Configuration and Functions

PW, DB Package
16-Pin TSSOP, SSOP
Top View
TCA9538 po_cps199.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
A0 1 I Address input. Connect directly to VCC or ground
A1 2 I Address input. Connect directly to VCC or ground
GND 8 — Ground
INT 13 O Interrupt output. Connect to VCC through a pull-up resistor
P0 4 I/O P-port input-output. Push-pull design structure. At power on, P0 is configured as an input
P1 5 I/O P-port input-output. Push-pull design structure. At power on, P1 is configured as an input
P2 6 I/O P-port input-output. Push-pull design structure. At power on, P2 is configured as an input
P3 7 I/O P-port input-output. Push-pull design structure. At power on, P3 is configured as an input
P4 9 I/O P-port input-output. Push-pull design structure. At power on, P4 is configured as an input
P5 10 I/O P-port input-output. Push-pull design structure. At power on, P5 is configured as an input
P6 11 I/O P-port input-output. Push-pull design structure. At power on, P6 is configured as an input
P7 12 I/O P-port input-output. Push-pull design structure. At power on, P7 is configured as an input
RESET 3 I Active-low reset input. Connect to VCC through a pull-up resistor if no active connection is used
SCL 14 I Serial clock bus. Connect to VCC through a pull-up resistor
SDA 15 I/O Serial data bus. Connect to VCC through a pull-up resistor
VCC 16 — Supply voltage

6 Specifications

6.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage –0.5 6 V
VI Input voltage (2) –0.5 6 V
VO Output voltage(2) –0.5 6 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –20 mA
IIOK Input-output clamp current VO < 0 or VO > VCC ±20 mA
IOL Continuous output low current through a single P-port VO = 0 to VCC 50 mA
IOH Continuous output high current through a single P-port VO = 0 to VCC –50 mA
ICC Continuous current through GND by all P-ports, INT, and SDA 250 mA
Continuous current through VCC by all P-ports –160
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VIH High-level input voltage SCL, SDA VCC = 1.65 V to 5.5 V 0.7 × VCC VCC(1) V
A0, A1, RESET, P7–P0 VCC = 1.65 V to 2.7 V 0.7 × VCC 5.5
VCC = 3 V to 5.5 V 0.8 × VCC 5.5
VIL Low-level input voltage SCL, SDA VCC = 1.65 V to 5.5 V –0.5 0.3 × VCC V
A0, A1, RESET, P7–P0 VCC = 1.65 V to 2.7 V –0.5 0.3 × VCC
VCC = 3 V to 5.5 V –0.5 0.2 × VCC
IOL Low-level output current Any P-port, P7–P0 25 mA
IOH High-level output current Any P-port, P7–P0 –10 mA
ICC Continuous current through GND All P-ports P7-P0, INT, and SDA 200 mA
Continuous current through VCC All P-ports P7-P0 –80
TA Operating free-air temperature –40 85 °C
(1) The SCL and SDA pins shall not be at a higher potential than the supply voltage VCC in the application, or an increase in supply current, ICC, will result.

6.4 Thermal Information

THERMAL METRIC(1) TCA9538 UNIT
PW (TSSOP) DB (SSOP)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 122 113.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56.4 63.6 °C/W
RθJB Junction-to-board thermal resistance 67.1 64 °C/W
ψJT Junction-to-top characterization parameter 10.8 21.2 °C/W
ψJB Junction-to-board characterization parameter 66.5 63.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VIK Input diode clamp voltage II = –18 mA 1.65 V to 5.5 V –1.2 V
VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.2 1.5 V
VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 0.75 1 V
VOH P-port high-level output voltage(4) IOH = –8 mA 1.65 V 1.2 V
2.3 V 1.8
3 V 2.6
4.5 V 4.1
IOH = –10 mA 1.65 V 1.1
2.3 V 1.7
3 V 2.5
4.5 V 4
IOL SDA (2) VOL = 0.4 V 1.65 V to 5.5 V 3 11 mA
P port(5) VOL = 0.5 V 1.65 V 8 10
2.3 V 8 13
3 V 8 15
4.5 V 8 17
VOL = 0.7 V 1.65 V 10 14
2.3 V 10 17
3 V 10 20
4.5 V 10 24
INT (3) VOL = 0.4 V 1.65 V to 5.5 V 3 7
II SCL, SDA VI = VCC or GND 1.65 V to 5.5 V ±1 μA
A0, A1, RESET ±1
IIH P port VI  = VCC 1.65 V to 5.5 V 1 μA
IIL P port VI  = GND 1.65 V to 5.5 V –1 μA
ICC Operating mode VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 400 kHz, No load
tr = 3 ns		 5.5 V 18 30 μA
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 400 kHz, No load
tr,max = 300 ns		 5.5 V 34
3.6 V 15
2.7 V 9
1.65 V 5
VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 100 kHz, No load
tr,max = 1 µs		 5.5 V 20
3.6 V 8
2.7 V 5
1.65 V 3
Standby mode VI = VCC or GND, IO = 0,
I/O = inputs, fscl = 0 kHz, No load		 5.5 V 1.9 3.5 μA
3.6 V 1.1 1.8
2.7 V 1 1.6
1.65 V 0.4 1
ΔICC Additional current in standby mode One P-port input at VCC  – 0.6 V,
Other P-port inputs at VCC or GND		 1.65 V to 5.5 V 70 µA
Ci SCL VI = VCC or GND 1.65 V to 5.5 V 4 5 pF
Cio SDA VIO = VCC or GND 1.65 V to 5.5 V 5.5 6.5 pF
P port 8 9.5
(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
(2) The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.
(3) The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.
(4) Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os (P-ports P7-P0) through VCC must be limited to a maximum current of 80 mA.
(5) Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.

6.6 I2C Interface Timing Requirements

over operating free-air temperature range (unless otherwise noted) (see Figure 9)
MIN MAX UNIT
STANDARD MODE
fscl I2C clock frequency 0 100 kHz
tsch I2C clock high time 4 μs
tscl I2C clock low time 4.7 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 250 ns
tsdh I2C serial-data hold time 0 ns
ticr I2C input rise time 1000 ns
ticf I2C input fall time 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 300 ns
tbuf I2C bus free time between Stop and Start 4.7 μs
tsts I2C Start or repeated Start condition setup 4.7 μs
tsth I2C Start or repeated Start condition hold 4 μs
tsps I2C Stop condition setup 4 μs
tvd(data) Valid data time SCL low to SDA output valid 3.45 μs
tvd(ack) Valid data time of ACK condition ACK signal from SCL low to
SDA (out) low		 3.45 μs
Cb I2C bus capacitive load 400 ns
FAST MODE
fscl I2C clock frequency 0 400 kHz
tsch I2C clock high time 0.6 μs
tscl I2C clock low time 1.3 μs
tsp I2C spike time 50 ns
tsds I2C serial-data setup time 100 ns
tsdh I2C serial-data hold time 0 ns
ticr I2C input rise time 20 300 ns
ticf I2C input fall time 20 × (VDD / 5.5 V) 300 ns
tocf I2C output fall time 10-pF to 400-pF bus 20 × (VDD / 5.5 V) 300 ns
tbuf I2C bus free time between Stop and Start 1.3 μs
tsts I2C Start or repeated Start condition setup 0.6 μs
tsth I2C Start or repeated Start condition hold 0.6 μs
tsps I2C Stop condition setup 0.6 μs
tvd(data) Valid data time SCL low to SDA output valid 0.9 μs
tvd(ack) Valid data time of ACK condition ACK signal from SCL low to
SDA (out) low		 0.9 μs
Cb I2C bus capacitive load 400 ns

6.7 RESET Timing Requirements

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
STANDARD and FAST MODE
tw Reset pulse duration 4 ns
tREC Reset recovery time 0 ns
tRESET Time to reset; VCC = 2.3 V-5.5 V 400 ns
Time to reset; VCC = 1.65 V-2.3 V 550

6.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 MIN MAX UNIT
STANDARD and FAST MODE
tiv Interrupt valid time P port INT 4 μs
tir Interrupt reset delay time SCL INT 4 μs
tpv Output data valid; VCC = 2.3 V-5.5 V SCL P7–P0 200 ns
Output data valid; VCC = 1.65 V-2.3 V 300
tps Input data setup time P port SCL 100 ns
tph Input data hold time P port SCL 1 μs

6.9 Typical Characteristics

TA = 25°C (unless otherwise noted)
TCA9538 D001_SCPS199.gif
fSCL = 400 kHz I/Os = High or Low Inputs
Figure 1. Supply Current (ICC, Operating Mode) vs Temperature (TA) at Four Supply Voltages
TCA9538 D003_SCPS199.gif
fSCL = 400 kHz I/Os = High or Low Inputs TA = 25°C
Figure 3. Supply Current (ICC, Operating Mode) vs Supply Voltage (VCC)
TCA9538 D005_SCPS199.gif
TA = 25°C
Figure 5. Sink Current (IOL) vs Output Low Voltage (VOL) for P-Ports at Four Supply Voltages
TCA9538 D007_SCPS199.gif
TA = 25°C
Figure 7. Source Current (IOH) vs Output High Voltage (VOH) for P-Ports at Four Supply Voltages
TCA9538 D002_SCPS199.gif
fSCL = 0 kHz I/Os = High or Low Inputs
Figure 2. Supply Current (ICC, Standby Mode) vs Temperature (TA) at Four Supply Voltages
TCA9538 D004_SCPS199.gif
I/Os = High or Low Inputs
Figure 4. Output Low Voltage (VOL) vs Temperature (TA) for P-Port I/Os
TCA9538 D006_SCPS199.gif
Figure 6. Output High Voltage (VCC – VOH) vs Temperature (TA) for P-Ports
TCA9538 D008_SCPS199.gif
TA = 25°C
Figure 8. Output High Voltage (VOH) vs Supply Voltage (VCC) for P-Ports

 
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