SCPS199 Data sheet

SCPS199D August 2014 – October 2016 TCA9538

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

PW|16
- MPDS361A
DB|16
- MPDS507A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8 Detailed Description

8.1 Overview

The TCA9538 is an 8-bit I/O expander for the two-line bidirectional bus (I²C) is designed for 1.65-V to 5.5-V V_CC operation. It provides general-purpose remote I/O expansion for most micro-controller families via the I²C interface (serial clock, SCL, and serial data, SDA, pins).

The TCA9538 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The INT pin can be connected to the interrupt input of a micro-controller. By sending an interrupt signal on this line, the remote I/O can inform the micro-controller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9538 can remain a simple slave device. The device outputs (latched) have high-current drive capability for directly driving LEDs.

Two hardware pins (A0 and A1) are used to program and vary the fixed I²C slave address and allow up to four devices to share the same I²C bus or SMBus.

The system master can reset the TCA9538 in the event of a timeout or other improper operation by asserting a low on the RESET input pin or by cycling the power supply and causing a power-on reset (POR). A reset puts the registers in their default state and initializes the I²C /SMBus state machine. The RESET feature and a POR cause the same reset/initialization to occur, but the RESET feature does so without powering down the part.

The TCA9538 consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master.

The TCA9538 is identical to the TCA9554 except for the removal of the internal I/O pull-up resistors, which greatly reduces power consumption when the I/Os are held LOW, the replacement of A2 with RESET, and different slave address range.

8.2 Functional Block Diagram

Pin numbers shown are for the PW package.

Figure 13. Functional Block Diagram

At power-on reset, all registers return to default values.

Figure 14. Simplified Schematic of P0 to P7

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above V_CC to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In this case, there are low impedance paths between the I/O pin and either V_CC or GND. The external voltage applied to this I/O pin must not exceed the recommended levels for proper operation.

8.3.2 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of any P-port I/O configured as an input. After time t_iv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the ports is changed back to the original state or when data is read from the Input Port register. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as an interrupt on the INT pin.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register.

The INT output has an open-drain structure and requires pull-up resistor to V_CC.

8.3.3 RESET Input

The RESET input can be asserted to reset the system while keeping the V_CC at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TCA9538 registers and I²C/SMBus state machine are changed to their default states once RESET is low (0). Once RESET is high (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pull-up resistor to V_CC if no active connection is used.

8.4 Device Functional Modes

8.4.1 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9538 in a reset condition until V_CC has reached V_PORR. At that point, the reset condition is released and the TCA9538 registers and SMBus/I²C state machine initialize to their default states. After that, V_CC must be lowered to below V_PORF and then back up to the operating voltage for a power-on reset cycle.

8.5 Programming

8.5.1 I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 15). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0–A1) of the slave device must not be changed between the Start and the Stop conditions.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 16).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 15).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 17). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

Figure 15. Definition of Start and Stop Conditions

Figure 16. Bit Transfer

Figure 17. Acknowledgment on I²C Bus

Table 1 shows the TCA9538 interface definition.

Table 1. Interface Definition Table

BYTE	BIT
BYTE	7 (MSB)	6	5	4	3	2	1	0 (LSB)
I²C slave address	H	H	H	L	L	A1	A0	R/W
Px I/O data bus	P7	P6	P5	P4	P3	P2	P1	P0

8.6 Register Map

8.6.1 Device Address

Figure 18 shows the address byte of the TCA9538.

Figure 18. TCA9538 Address

Table 2 shows the Address Reference of the TCA9538.

Table 2. Address Reference Table

INPUTS		I²C BUS SLAVE ADDRESS
A1	A0	I²C BUS SLAVE ADDRESS
L	L	112 (decimal), 70 (hexadecimal)
L	H	113 (decimal), 71 (hexadecimal)
H	L	114 (decimal), 72 (hexadecimal)
H	H	115 (decimal), 73 (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the TCA9538 (see Figure 19). Two bits of this command byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that is affected. This register can be written or read through the I²C bus. The command byte is sent only during a write transmission.

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent.

Figure 19. Control Register Bits

Table 3 shows the TCA9538 Command byte.

Table 3. Command Byte Table

CONTROL REGISTER BITS		COMMAND BYTE (HEX)	REGISTER	PROTOCOL	POWER-UP DEFAULT
B1	B0	COMMAND BYTE (HEX)	REGISTER	PROTOCOL	POWER-UP DEFAULT
0	0	0x00	Input Port	Read byte	XXXX XXXX
0	1	0x01	Output Port	Read/write byte	1111 1111
1	0	0x02	Polarity Inversion	Read/write byte	0000 0000
1	1	0x03	Configuration	Read/write byte	1111 1111

8.6.3 Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I²C device that the Input Port register is accessed next. See Table 4.

Table 4. Register 0 (Input Port Register) Table

BIT	I7	I6	I5	I4	I3	I2	I1	I0
DEFAULT	X	X	X	X	X	X	X	X

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See Table 5.

Table 5. Register 1 (Output Port Register) Table

BIT	O7	O6	O5	O4	O3	O2	O1	O0
DEFAULT	1	1	1	1	1	1	1	1

The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 6.

Table 6. Register 2 (Polarity Inversion Register) Table

BIT	N7	N6	N5	N4	N3	N2	N1	N0
DEFAULT	0	0	0	0	0	0	0	0

The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. See Table 7.

Table 7. Register 3 (Configuration Register) Table

BIT	C7	C6	C5	C4	C3	C2	C1	C0
DEFAULT	1	1	1	1	1	1	1	1

8.6.3.1 Bus Transactions

Data is exchanged between the master and the TCA9538 through write and read commands.

8.6.3.1.1 Writes

Data is transmitted to the TCA9538 by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 18 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte (see Figure 20 and Figure 21). There is no limitation on the number of data bytes sent in one write transmission.

Figure 20. Write to Output Port Register

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Figure 21. Write to Configuration or Polarity Inversion Registers

8.6.3.1.2 Reads

The bus master first must send the TCA9538 address with the LSB set to a logic 0 (see Figure 18 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the TCA9538 (see Figure 22 and Figure 23). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data.

Figure 22. Read From Register