Reading from a target is very similar to writing, but requires some additional steps. In order to read from a target, the controller must first instruct the target which register it wishes to read from. This is done by the controller starting off the transmission in a similar fashion as the write, by sending the address with the R/ W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. When the target acknowledges this register address, the controller sends a START condition again, followed by the target address with the R/ W bit set to 1 (signifying a read). This time, the target acknowledges the read request, and the controller releases the SDA bus but continues supplying the clock to the target. During this part of the transaction, the controller becomes the controller-receiver, and the target becomes the target-transmitter.

The controller continues to send out the clock pulses, but releases the SDA line so that the target can transmit data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that it is ready for more data. When the controller has received the number of bytes it is expecting, it sends a NACK, signaling to the target to halt communications and release the bus. The controller follows this up with a STOP condition.

If a read is requested by the controller after a POR without first setting the command byte via a write, the device NACKs until a command byte-register address is set as described above.

See the Section 8.6.2 section to see list of the TCA9539-Q1s internal registers and a description of each one.

Figure 8-10 shows an example of reading a single byte from a target register.

Figure 8-10 Read from Register

When a restart occurs after a single write request to a register, the requested register is used for the read request. Note that when reading multiple bytes of data. Data is clocked into the register on the rising edge of the ACK clock pulse before data is sent. The internal register value is also changed to the other register of the pair on the rising edge of the ACK clock pulse before data is sent. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. If a restart occurs during a read, the data is lost because the internal register already has been changed to the next register in the pair.

There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus controller must not acknowledge the data. Figure 8-11 and Figure 8-12 show two different scenarios of Read Input Port Register.

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).

This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual data transfer from the P port (see the Section 8.6.3.1.2 section for these details).

Figure 8-11 Read Input Port Register, Scenario 1

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).

This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual data transfer from the P port (see the Section 8.6.3.1.2 section for these details).

Figure 8-12 Read Input Port Register, Scenario 2