SCPS254D January   2014  – October 2021 TCA9539-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 RESET Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 RESET Input
      3. 8.3.3 Interrupt ( INT) Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register And Command Byte
      3. 8.6.3 Register Descriptions
        1. 8.6.3.1 Bus Transactions
          1. 8.6.3.1.1 Writes
          2. 8.6.3.1.2 Reads
  9. 9 Power Supply Recommendations
    1. 9.1 Power-On Reset Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9539-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The voltage waveform for a power-on reset is shown in Figure 9-1.

GUID-CFB5FD73-C7C0-4C7A-A125-55BEE23002A3-low.gifFigure 9-1 VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC

Table 9-1 specifies the performance of the power-on reset feature for TCA9539-Q1.

Table 9-1 Recommended Supply Sequencing And Ramp Rates (1)
PARAMETERMINTYPMAXUNIT
VCC_FTFall rateSee Figure 9-10.1ms
VCC_RTRise rateSee Figure 9-10.1ms
VCC_TRRTime to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND)See Figure 9-12μs
VCC_GHThe level (referenced to VCC) that VCC can glitch down to, but not cause a functional disruption when VCC_GWSee Figure 9-21.2V
VCC_MVThe minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated)See Figure 9-21.5V
VCC_GWGlitch width that does not cause a functional disruptionSee Figure 9-210μs
VPORFVoltage trip point of POR on falling VCC0.751V
VPORRVoltage trip point of POR on rising VCC1.21.5V
(1) TA = –40°C to +125°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-2 and Table 9-1 provide more information on how to measure these specifications.

GUID-CE756D35-2D63-4E70-845E-01FA23BDEDF4-low.gifFigure 9-2 Glitch Width, Glitch Height, and Minimum Glitch Voltage

VPOR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 9-3 and Table 9-1 provide more details on this specification.

GUID-1EE3FBAF-4CDA-4948-A610-DF349B479218-low.gifFigure 9-3 VPOR