SCPS202C October   2009  – May 2016 TCA9539

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 RESET Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 RESET Input
      3. 8.3.3 Interrupt (INT) Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
        1. 8.6.3.1 Bus Transactions
          1. 8.6.3.1.1 Writes
          2. 8.6.3.1.2 Reads
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 9.2.1.2 Minimizing ICC When I/Os Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
24-Pins TSSOP
Top View
TCA9539 po_cps202.gif
RTW, RGE Package
24-Pins WQFN, VQFN
Top View
TCA9539 po__rtw_cps202.gif

Pin Functions

NAME NO. I/O DESCRIPTION
TSSOP
(PW)		 QFN
(RTW, RGE)
A0 21 18 I Address input. Connect directly to VCC or ground
A1 2 23 I Address input. Connect directly to VCC or ground
GND 12 9 — Ground
INT 1 22 O Interrupt open-drain output. Connect to VCC through a pull-up resistor
RESET 3 24 I Active-low reset input. Connect to VCC through a pull-up resistor if no active connection is used
P00 4 1 I/O P-port input-output. Push-pull design structure. At power on, P00 is configured as an input
P01 5 2 I/O P-port input-output. Push-pull design structure. At power on, P01 is configured as an input
P02 6 3 I/O P-port input-output. Push-pull design structure. At power on, P02 is configured as an input
P03 7 4 I/O P-port input-output. Push-pull design structure. At power on, P03 is configured as an input
P04 8 5 I/O P-port input-output. Push-pull design structure. At power on, P04 is configured as an input
P05 9 6 I/O P-port input-output. Push-pull design structure. At power on, P05 is configured as an input
P06 10 7 I/O P-port input-output. Push-pull design structure. At power on, P06 is configured as an input
P07 11 8 I/O P-port input-output. Push-pull design structure. At power on, P07 is configured as an input
P10 13 10 I/O P-port input-output. Push-pull design structure. At power on, P10 is configured as an input
P11 14 11 I/O P-port input-output. Push-pull design structure. At power on, P11 is configured as an input
P12 15 12 I/O P-port input-output. Push-pull design structure. At power on, P12 is configured as an input
P13 16 13 I/O P-port input-output. Push-pull design structure. At power on, P13 is configured as an input
P14 17 14 I/O P-port input-output. Push-pull design structure. At power on, P14 is configured as an input
P15 18 15 I/O P-port input-output. Push-pull design structure. At power on, P15 is configured as an input
P16 19 16 I/O P-port input-output. Push-pull design structure. At power on, P16 is configured as an input
P17 20 17 I/O P-port input-output. Push-pull design structure. At power on, P17 is configured as an input
SCL 22 19 I Serial clock bus. Connect to VCC through a pull-up resistor
SDA 23 20 I/O Serial data bus. Connect to VCC through a pull-up resistor
VCC 24 21 — Supply voltage