SLLSEV0G November 2017 – December 2024 TCAN1043-Q1 , TCAN1043G-Q1 , TCAN1043H-Q1 , TCAN1043HG-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY CHARACTERISTICS | |||||||
ISUP | Supply current VSUP | Normal, Silent, Go-to-Sleep | 40 | 70 | µA | ||
Standby mode | Standby mode, VCC > 4.5 V, VIO > 2.8 V, VINH = V(WAKE) = VSUP | 15 | 45 | µA | |||
Sleep mode | Sleep mode, VCC = VIO = VINH = 0 V V(WAKE) = VSUP | 15 | 30 | µA | |||
ICC | Supply current Normal mode VCC | Dominant | See Figure 7-2. TXD = 0 V, RL = 60 Ω, CL = open. Typical bus load. | 70 | mA | ||
See Figure 7-2. TXD = 0 V, RL = 50 Ω, CL = open. High bus load. | 80 | mA | |||||
Dominant with bus fault | See Figure 7-2. TXD = 0 V, CANH = -25 V, RL = open, CL = open | 110 | mA | ||||
Recessive | See Figure 7-2. TXD = VIO, RL = 50 Ω, CL = open, RCM = open | 5 | mA | ||||
Supply current Silent and Go-to-Sleep mode | See Figure 7-2. TXD = VIO, RL = 50 Ω, CL = open | 2.5 | mA | ||||
Supply current Standby mode | See Figure 7-2. EN = L, NSTB = L | 5 | µA | ||||
Sleep mode | See Figure 7-2. EN = H or L, NSTB = L | 5 | |||||
IIO | I/O supply current | Normal mode | RXD floating, TXD = 0 V (dominant) nSTB = VIO, EN = VIO | 450 | µA | ||
Normal, Silent or Go-to-Sleep mode | RXD floating, TXD = VIO recessive | 5 | µA | ||||
µA | |||||||
Sleep mode | NSTB = L | 5 | µA | ||||
UVSUP | Undervoltage detection on VSUP for protected mode | 3.0 | 4.2 | V | |||
VHYS(UVSUP) | Hysteresis voltage on UVSUP | 50 | mV | ||||
UVVCC | Rising undervoltage detection on VCC for protected mode | 4.1 | 4.4 | V | |||
Falling undervoltage detection on VCC for protected mode | 3.5 | 3.9 | V | ||||
VHYS(UVVCC) | Hysteresis voltage on UVVCC | 200 | mV | ||||
UVVIO | Undervoltage detection on VIO for protected mode | 1.3 | 2.75 | V | |||
VHYS(UVIO) | Hysteresis voltage on UVIO | 80 | mV | ||||
Driver Electrical Characteristics | |||||||
VO(D) | Bus output voltage dominant - normal mode | CANH | See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 50 ≤ RL ≤ 65 Ω, CL = open, RCM = open | 2.75 | 4.5 | V | |
CANL | 0.5 | 2.25 | V | ||||
VO(R) | Bus output voltage recessive | CANH and CANL | See Figure 7-2 and Figure 8-3, TXD = VCC, VIO = VCC, Normal or Silent(2), RL = open, RCM = open | 2 | 0.5 × VCC | 3 | V |
VOD(D) | Differential output voltage dominant | CANH - CANL | See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open | 1.5 | 3 | V | |
See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 45 Ω ≤ RL ≤ 50 Ω, CL = open, RCM = open | 1.4 | 3 | V | ||||
See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, RL = 2240 Ω, CL = open, RCM = open | 1.5 | 5 | V | ||||
See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 45 Ω ≤ RL ≤ 70 Ω, CL = open, RCM = open | 1.4 | 3.3 | V | ||||
VOD(R) | Differential output voltage recessive | CANH - CANL | See Figure 7-2 and Figure 8-3, TXD = VCC, Normal or Silent mode(2), RL = 60 Ω, CL = open, RCM = open | –120 | 12 | mV | |
See Figure 7-2 and Figure 8-3, TXD = VCC, Normal or Silent mode(2), RL = open, CL = open, RCM = open | –50 | 50 | mV | ||||
VSYM | Driver symmetry, dominant or recessive VSYM = (VO(CANH) + VO(CANL))/VCC | See Figure 7-2 and Figure 9-4, Normal mode, CL = open, RCM = open, TXD = 1MHz(3) | 0.9 | 1.1 | V / V | ||
VSYM_DC | Driver symmetry, dominant VSYM(DC) = VCC - VO(CANH) - VO(CANL) | See Figure 7-2 and Figure 8-3, Normal or Silent mode, RL = 60 Ω, CL = open, RCM = open | –400 | 400 | mV | ||
IOS(DOM) | Short circuit steady-state output current dominant | See Figure 7-10 and Figure 8-3, VCANH = -5 V, CANL = open, TXD = 0 V | –100 | mA | |||
See Figure 7-10 and Figure 8-3, VCANL = 40 V, CANH = open, TXD = 0 V | 100 | mA | |||||
IOS(REC) | Short circuit steady-state output current recessive | See Figure 7-10 and Figure 8-3 –27 V ≤ VBUS ≤ 32 V, VBUS = CANH = CANL, TXD = VIO | –5 | 5 | mA | ||
VO(STB) | Bus output voltage Standby mode | CANH | STB = VCC or VIO, RL = open, RCM = open | –0.1 | 0 | 0.1 | V |
CANL | –0.1 | 0 | 0.1 | V | |||
CANH - CANL | –0.2 | 0 | 0.2 | V | |||
Receiver Electrical Characteristics | |||||||
VCM | Common mode range Normal and Silent modes | See Figure 7-3 and Table 8-5 | -30 | 30 | V | ||
VIT | Input threshold voltage Normal and Silent modes | See Figure 7-3 and Table 8-5, VCM ≤ ±20 V | 500 | 900 | mV | ||
See Figure 7-3 and Table 8-5, VCM ≤ ±30 V | 400 | 1000 | mV | ||||
VREC | Receiver recessive voltage | See Figure 7-3 and Table 8-5 Normal or Silent mode, VCM = ±20 V | -3 | 0.5 | V | ||
VDOM | Receiver dominant voltage | 0.9 | 8 | V | |||
VHYS | Hysteresis voltage for input threshold Normal and Silent modes | See Figure 7-3 and Table 8-5 | 120 | mV | |||
VIT(Sleep) | Input threshold Sleep mode | See Figure 7-3 and Table 8-5; VCM = ± 12 V | 400 | 1150 | mV | ||
VREC(Sleep) | Receiver recessive voltage Sleep mode | -3 | 0.4 | V | |||
VDOM(Sleep) | Receiver dominant voltage Sleep mode | 1.15 | 8 | V | |||
VCM | Common mode range Standby, Go-to-Sleep and Sleep modes | See Figure 7-3 and Table 8-5 | -12 | 12 | V | ||
IIOFF(LKG) | Power-off (unpowered) bus input leakage current | CANH = CANL = 5 V, VCC = GND, VIO = GND, VSUP = 0 V | 4.8 | µA | |||
CI | Input capacitance to ground (CANH or CANL) | TXD = VCC, VIO = VCC(4) | 24 | 30 | pF | ||
CID | Differential input capacitance (CANH or CANL) | 12 | 15 | pF | |||
RID | Differential input resistance | TXD = VCC = VIO = 5 V, Normal mode; -30 ≤ VCM ≤ +30V | 30 | 80 | kΩ | ||
RIN | Input resistance (CANH or CANL) | 15 | 40 | kΩ | |||
RIN(M) | Input resistance matching: [1 – RIN(CANH) / RIN(CANL)] × 100% | V(CANH) = V(CANL) = 5 V | –2% | 2% | |||
RCBF | Valid differential load impedance range for bus fault circuitry | RCM = RL, CL = open | 45 | 70 | Ω | ||
TXD TERMINAL (CAN TRANSMIT DATA INPUT) | |||||||
VIH | High level input voltage | 0.7 VIO | V | ||||
VIL | Low level input voltage | 0.3 VIO | V | ||||
IIH | High level input leakage current | TXD = VCC = VIO = 5.5 V | –2.5 | 0 | 1 | µA | |
IIL | Low level input leakage current | TXD = 0 V, VCC = VIO = 5.5 V | –100 | –2.5 | µA | ||
ILKG(OFF) | Unpowered leakage current | TXD = 5.5 V, VCC = VIO = 0 V | –1 | 0 | 1 | µA | |
CI | Input capacitance | VIN = 0.4 x sin(2 x π x 2 x 106 x t) + 2.5 V | 5 | pF | |||
RXD TERMINAL (CAN RECEIVE DATA OUTPUT) | |||||||
VOH | High level output voltage | See Figure 7-3, IO = –2 mA. | 0.8 VIO | V | |||
VOL | Low level output voltage | See Figure 7-3, IO = –2 mA. | 0.2 VIO | V | |||
nFAULT TERMINAL (FAULT AND STATUS OUTPUT) | |||||||
VOH | High level output voltage | See Figure 7-1, IO = –2 mA. | 0.8 VIO | V | |||
VOL | Low level output voltage | See Figure 7-1 IO = 2 mA. | 0.2 VIO | V | |||
nSTB TERMINAL (STANDBY MODE INPUT) | |||||||
VIH | High level input voltage | 0.7 VIO | V | ||||
VIL | Low level input voltage | 0.3 VIO | V | ||||
IIH | High level input leakage current | nSTB = VCC = VIO = 5.5 V | 0.5 | 10 | µA | ||
IIL | Low level input leakage current | nSTB = 0 V, VCC = VIO = 5.5 V | –1 | 1 | µA | ||
ILKG(OFF) | Unpowered leakage current | nSTB = 5.5 V, VCC = 0 V, VIO = 0 V | –1 | 0 | 1 | µA | |
EN TERMINAL (ENABLE MODE INPUT) | |||||||
VIH | High level input voltage | 0.7 VIO | V | ||||
VIL | Low level input voltage | 0.3 VIO | V | ||||
IIH | High level input leakage current | EN = VCC = VIO = 5.5 V | 0.5 | 10 | µA | ||
IIL | Low level input leakage current | EN = 0 V, VCC = VIO = 5.5 V | –1 | 1 | µA | ||
ILKG(OFF) | Unpowered leakage current | EN = 5.5 V, VCC = 0 V, VIO = 0 V | –1 | 0 | 1 | µA | |
INH TERMINAL (INHIBIT OUTPUT) | |||||||
ΔVH | High level voltage drop INH with respect to VSUP | IINH = –0.5 mA | 0.5 | 1 | V | ||
ILKG(INH) | Leakage current | INH = 0 V, Sleep Mode | -5 | 5 | µA | ||
Wake TERMINAL (WAKE INPUT) | |||||||
VIH | High level input voltage | Standby and Sleep Mode | VSUP - 1.9 | V | |||
VIL | Low level input voltage | Standby and Sleep Mode | VSUP - 3.5 | V | |||
IIH | High level input current(5) | WAKE = VSUP – 1 V | –25 | –15 | µA | ||
IIL | Low level input current(5) | WAKE = 1 V | 15 | 25 | µA |