SLLSFV8A July   2024  – November 2024 TCAN1043N-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings - IEC Specifications
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation Ratings
    7. 5.7  Power Supply Characteristics
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply Pins
        1. 7.3.1.1 VSUP Pin
        2. 7.3.1.2 VCC Pin
        3. 7.3.1.3 VIO Pin
      2. 7.3.2 Digital Inputs and Outputs
        1. 7.3.2.1 TXD Pin
        2. 7.3.2.2 RXD Pin
        3. 7.3.2.3 nFAULT Pin
        4. 7.3.2.4 EN Pin
        5. 7.3.2.5 nSTB Pin
      3. 7.3.3 GND
      4. 7.3.4 INH Pin
      5. 7.3.5 WAKE Pin
      6. 7.3.6 CAN Bus Pins
      7. 7.3.7 Faults
        1. 7.3.7.1 Internal and External Fault Indicators
          1. 7.3.7.1.1 Power-Up (PWRON Flag)
          2. 7.3.7.1.2 Wake-Up Request (WAKERQ Flag)
          3. 7.3.7.1.3 Undervoltage Faults
            1. 7.3.7.1.3.1 Undervoltage on VSUP
            2. 7.3.7.1.3.2 Undervoltage on VCC
            3. 7.3.7.1.3.3 Undervoltage on VIO
          4. 7.3.7.1.4 CAN Bus Fault (CBF Flag)
          5. 7.3.7.1.5 TXD Dominant State Timeout (TXDDTO Flag)
          6. 7.3.7.1.6 TXD Shorted to RXD Fault (TXDRXD Flag)
          7. 7.3.7.1.7 CAN Bus Dominant Fault (CANDOM Flag)
      8. 7.3.8 Local Faults
        1. 7.3.8.1 TXD Dominant Timeout (TXD DTO)
        2. 7.3.8.2 Thermal Shutdown (TSD)
        3. 7.3.8.3 Undervoltage Lockout (UVLO)
        4. 7.3.8.4 Unpowered Devices
        5. 7.3.8.5 Floating Terminals
        6. 7.3.8.6 CAN Bus Short-Circuit Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Mode Description
        1. 7.4.1.1 Normal Mode
        2. 7.4.1.2 Silent Mode
        3. 7.4.1.3 Standby Mode
        4. 7.4.1.4 Go-To-Sleep Mode
        5. 7.4.1.5 Sleep Mode
          1. 7.4.1.5.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 7.4.1.5.2 Local Wake-Up (LWU) via WAKE Input Terminal
      2. 7.4.2 CAN Transceiver
        1. 7.4.2.1 CAN Transceiver Operation
          1. 7.4.2.1.1 CAN Transceiver Modes
            1. 7.4.2.1.1.1 CAN Off Mode
            2. 7.4.2.1.1.2 CAN Autonomous: Inactive and Active
            3. 7.4.2.1.1.3 CAN Active
          2. 7.4.2.1.2 Driver and Receiver Function Tables
          3. 7.4.2.1.3 CAN Bus States
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Design Requirements
        1. 8.1.2.1 Bus Loading, Length and Number of Nodes
      3. 8.1.3 Detailed Design Procedure
        1. 8.1.3.1 CAN Termination
      4. 8.1.4 Application Curves
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.10 Switching Characteristics

Over recommended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12 V, VIO = 3.3 V, VCC = 5 V and RL = 60 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver Characteristics
tprop(TxD-busrec)  Propagation delay time, high TXD to driver recessive Propagation delay time, high TXD to driver recessive RL = 60 Ω, CL = 100 pF, RCM = open
See Figure 6-4		 30 50 90 ns
tprop(TxD-busdom) Propagation delay time, low TXD to driver dominant 30 50 90 ns
tsk(p) Pulse skew (|tpHR - tpLD|) 8 ns
tR Differential output signal rise time 50 ns
tF Differential output signal fall time 50 ns
tTXDDTO Dominant timeout TXD = 0 V, RL = 60 Ω, CL = open
See Figure 6-7		 1.2 3.8 ms
Receiver Characteristics
tprop(busrec-RxD)  Propagation delay time, bus recessive input to high RXD CL(RXD) = 15 pF
See Figure 6-5		 25 75 140 ns
tprop(busdom-RxD) Propagation delay time, bus dominant input to RXD low output 20 75 130 ns
tR Output signal rise time (RXD) 4 ns
tF Output signal fall time (RXD) 4 ns
tBUSDOM Dominant time out RL = 60 Ω, CL = open
See Figure 6-5		 1.4 3.8 ms
CAN FD Characteristics
tΔBIT(BUS)(1) Transmitted recessive bit width variation on CAN bus output pins with tBIT(TXD) = 500 ns Transmitted recessive bit width variation on CAN bus output pins with tBIT(TXD) = 500 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
tΔBit(BUS) = tBIT(BUS) -tBIT(TXD)
See Figure 6-6		 -50 25 ns
tΔBIT(BUS)(1) Transmitted recessive bit width variation on CAN bus output pins with tBIT(TXD) = 200 ns Transmitted recessive bit width variation on CAN bus output pins with tBIT(TXD) = 200 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
tΔBit(BUS) = tBIT(BUS) -tBIT(TXD)
See Figure 6-6		 -40 10 ns
tΔBIT(BUS)(1) Transmitted recessive bit width variation on CAN bus output pins with tBIT(TXD) = 125 ns Transmitted recessive bit width variation on CAN bus output pins with tBIT(TXD) = 125 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
tΔBit(BUS) = tBIT(BUS) -tBIT(TXD)
See Figure 6-6		 -45 10 ns
tΔBIT(RXD)(1) Received recessive bit width variation on RXD output pins with tBIT(TXD) = 500 ns Received recessive bit width variation on RXD output pins with tBIT(TXD) = 500 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
tΔBit(RXD) = tBIT(RXD) -tBIT(TXD)
See Figure 6-6		 -90 40 ns
tΔBIT(RXD)(1) Received recessive bit width variation on RXD output pins with tBIT(TXD) = 200 ns Received recessive bit width variation on RXD output pins with tBIT(TXD) = 200 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
tΔBit(RXD) = tBIT(RXD) -tBIT(TXD)
See Figure 6-6		 -70 20 ns
tΔBIT(RXD)(1) Received recessive bit width variation on RXD output pins with tBIT(TXD) =125 ns Received recessive bit width variation on RXD output pins with tBIT(TXD) = 125 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
tΔBit(RXD) = tBIT(RXD) -tBIT(TXD)
See Figure 6-6		 -65 20 ns
tΔREC(1) Receiver timing symmetry with tBIT(TXD) = 500 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 6-6		 –50 20 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 6-6		 –45 15 ns
Receiver timing symmetry with tBIT(TXD) = 125 ns(2) RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 6-6		 –25 10 ns
(1) The input signal on TXD shall have rise times and fall times (10% to 90%) of less than 10 ns
(2) Specified by design and verified via bench characterization