SLLSFL8A July   2021  – December 2021 TCAN1046AV-Q1 , TCAN1048AV-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  ESD Ratings — IEC Specifications
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Thermal Characteristics
    6. 8.6  Supply Characteristics
    7. 8.7  Dissipation Ratings
    8. 8.8  Electrical Characteristics
    9. 8.9  Switching Characteristics
    10. 8.10 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Pin Description
        1. 10.3.1.1 TXD1 and TXD2
        2. 10.3.1.2 GND1 and GND2
        3. 10.3.1.3 VCC
        4. 10.3.1.4 RXD1 and RXD2
        5. 10.3.1.5 VIO
        6. 10.3.1.6 CANH and CANL
        7. 10.3.1.7 STB1, STB2, nSTB1, and nSTB2 (Standby)
      2. 10.3.2 CAN Bus States
      3. 10.3.3 TXD Dominant Timeout (DTO)
      4. 10.3.4 CAN Bus Short Circuit Current Limiting
      5. 10.3.5 Thermal Shutdown (TSD)
      6. 10.3.6 Undervoltage Lockout
      7. 10.3.7 Unpowered Device
      8. 10.3.8 Floating pins
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operating Modes
      2. 10.4.2 Normal Mode
      3. 10.4.3 Standby Mode
        1. 10.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 10.4.4 Driver and Receiver Function
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 CAN Termination
      2. 11.2.2 Detailed Design Procedures
        1. 11.2.2.1 Bus Loading, Length and Number of Nodes
      3. 11.2.3 Application Curves
    3. 11.3 System Examples
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.9 Switching Characteristics

Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted); Parameters apply to both CAN channels
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Device Switching Characteristics
tPROP(LOOP1) Total loop delay
Driver input (TXD) to receiver output (RXD), recessive to dominant		 STB = 0 V / nSTB = VIO
VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 9-4 		125 210 ns
tPROP(LOOP1) Total loop delay
Driver input (TXD) to receiver output (RXD), recessive to dominant		 STB = 0 V / nSTB = VIO
VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 9-4 		165 255 ns
tPROP(LOOP2) Total loop delay
Driver input (TXD) to receiver output (RXD), dominant to recessive		 STB = 0 V / nSTB = VIO
VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 9-4 		150 210 ns
tPROP(LOOP2) Total loop delay
Driver input (TXD) to receiver output (RXD), dominant to recessive		 STB = 0 V / nSTB = VIO
VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 9-4 		180 255 ns
tMODE Mode change time, from normal to standby or from standby to normal See Figure 9-5 and Figure 9-6 20 µs
tWK_FILTER Filter time for a valid wake-up pattern See Figure 10-5 0.5 1.8 µs
tWK_TIMEOUT Bus wake-up timeout 0.8 6 ms
Driver Switching Characteristics
tpHR Propagation delay time, high TXD to driver recessive (dominant to recessive) STB = 0 V / nSTB = VIO
RL = 60 Ω, CL = 100 pF;
See Figure 9-2 		80 ns
tpLD Propagation delay time, low TXD to driver dominant (recessive to dominant) 70 ns
tsk(p) Pulse skew (|tpHR - tpLD|) 14 ns
tR Differential output signal rise time 28 ns
tF Differential output signal fall time 50 ns
tTXD_DTO Dominant timeout STB = 0 V / nSTB = VIO
RL = 60 Ω, CL = 100 pF;
See Figure 9-7 		1.2 4.0 ms
Receiver Switching Characteristics
tpRH Propagation delay time, bus recessive input to high output (dominant to recessive) STB = 0 V / nSTB = VIO
CL(RXD) = 15 pF
See Figure 9-3 		81 ns
tpDL Propagation delay time, bus dominant input to low output (recessive to dominant) 66 ns
tR RXD output signal rise time 10 ns
tF RXD output signal fall time 10 ns
FD Timing Characteristics
tBIT(BUS) Bit time on CAN bus output pins
tBIT(TXD) = 500 ns		 STB = 0 V / nSTB = VIO
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS) ;
See Figure 9-4 		450 525 ns
Bit time on CAN bus output pins
tBIT(TXD) = 200 ns		 160 205 ns
Bit time on CAN bus output pins
tBIT(TXD) = 125 ns(1) 		85 130 ns
tBIT(RXD) Bit time on RXD output pins
tBIT(TXD) = 500 ns		 410 540 ns
Bit time on RXD output pins
tBIT(TXD) = 200 ns		 130 210 ns
Bit time on RXD output pins
tBIT(TXD) = 125 ns(1) 		75 135 ns
tREC Receiver timing symmetry
tBIT(TXD) = 500 ns		 -50 20 ns
Receiver timing symmetry
tBIT(TXD) = 200 ns		 -40 10 ns
Receiver timing symmetry
tBIT(TXD) = 125 ns(1) 		-40 10 ns
(1) Measured during characterization and not an ISO 11898-2:2016 parameter.