Place the protection and filtering circuitry close to the bus connectors, J1 and J2, to prevent transients, ESD, and noise from propagating onto the board. This layout example shows optional transient voltage suppression (TVS) diodes, D1 and D2, which may be implemented if the system-level requirements exceed the specified rating of the transceiver. This example also shows optional bus filter capacitors C6, C8, C9, and C11.
Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.
Note:
High frequency current follows the path of least impedance and not the path of least resistance.
This layout example shows how split termination could be implemented on the CAN node. The termination is split into two pairs of resistors, R8, R9, R10, and R11, with the center or split tap of the termination connected to ground via capacitors C7 and C10. Split termination provides common mode filtering for the bus. See Section 9.2.1.1, Section 8.3.4, and Equation 2 for information on termination concepts and power ratings needed for the termination resistor(s).
To limit current of digital lines series resistors may be used. Examples are R2, R3, R5, R6, R7, and R12.
Pin 1 and pin 6 are shown for the TXD1 and TXD2 inputs of the device with R1 and R4 as optional pull-up resistors. If an open drain host controller is used this is mandatory to ensure the bit timing into the device is met.
Pin 8 and 14 are shown assuming the mode pin STB is used. If the device is only used in normal mode then only a pull-down resistor is needed.