SLLSET0D March   2016  – April 2021 TCAN1051-Q1 , TCAN1051G-Q1 , TCAN1051GV-Q1 , TCAN1051H-Q1 , TCAN1051HG-Q1 , TCAN1051HGV-Q1 , TCAN1051HV-Q1 , TCAN1051V-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings, Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Rating
    7. 6.7 Electrical Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TXD Dominant Timeout (DTO)
      2. 8.3.2 Thermal Shutdown (TSD)
      3. 8.3.3 Undervoltage Lockout
      4. 8.3.4 Unpowered Device
      5. 8.3.5 Floating Terminals
      6. 8.3.6 CAN Bus Short Circuit Current Limiting
      7. 8.3.7 Digital Inputs and Outputs
        1. 8.3.7.1 5-V VCC Only Devices (Devices without the "V" Suffix):
        2. 8.3.7.2 5 V VCC with VIO I/O Level Shifting (Devices with the "V" Suffix):
    4. 8.4 Device Functional Modes
      1. 8.4.1 CAN Bus States
      2. 8.4.2 Normal Mode
      3. 8.4.3 Silent Mode
      4. 8.4.4 Driver and Receiver Function Tables
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length and Number of Nodes
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 CAN Termination
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Switching Characteristics

Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
Device Switching Characteristics
tPROP(LOOP1)Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominantSee Figure 7-4, S = 0 V,
RL = 60 Ω,
CL = 100 pF, CL(RXD) = 15 pF		100160ns
tPROP(LOOP2)Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive110175
tMODEMode change time, from Normal to Silent or from Silent to NormalSee Figure 7-3110µs
Driver Switching Characteristics
tpHRPropagation delay time, high TXD to driver recessive (dominant to recessive)See Figure 7-1, S = 0 V,
RL = 60 Ω,
CL = 100 pF, RCM = open		75ns
tpLDPropagation delay time, low TXD to driver dominant (recessive to dominant)55
tsk(p)Pulse skew (|tpHR - tpLD|)20
tRDifferential output signal rise time45
tFDifferential output signal fall time45
SRDifferential output slew rate, dominant-to-recessive transition70V/µs
tTXD_DTODominant timeoutSee Figure 7-6, S = 0 V,
RL = 60 Ω, CL = open		1.23.8ms
Receiver Switching Characteristics
tpRHPropagation delay time, bus recessive input to high output (Dominant to Recessive)See Figure 7-2, S = 0 V,
CL(RXD) = 15 pF		65ns
tpDLPropagation delay time, bus dominant input to low output (Recessive to Dominant)50ns
tRRXD Output signal rise time10ns
tFRXD Output signal fall time10ns
FD Timing Parameters
tBIT(BUS)Bit time on CAN bus output pins with tBIT(TXD) = 500 ns, all devicesSee Figure 7-5 , S = 0 V,
RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF,
ΔtREC = tBIT(RXD) - tBIT(BUS)		435530ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns, G device variants only155210
tBIT(RXD)Bit time on RXD output pins with tBIT(TXD) = 500 ns, all devices400550
Bit time on RXD output pins with tBIT(TXD) = 200 ns, G device variants only120220
ΔtRECReceiver timing symmetry with tBIT(TXD) = 500 ns, all devices-6540
Receiver timing symmetry with tBIT(TXD) = 200 ns, G device variants only-4515
(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V (if applicable), RL = 60 Ω