SLLSFM8C February 2021 – October 2024 TCAN1057A-Q1
PRODUCTION DATA
The CAN bus has two logical states during operation: recessive and dominant. See Figure 7-1.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to VCC/2 via the high-resistance internal input resistors RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than the differential voltage of a single driver.