SLLSFM8C February   2021  – October 2024 TCAN1057A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings Table — IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Characteristics
    6. 5.6 Supply Characteristics
    7. 5.7 Dissipation Ratings
    8. 5.8 Electrical Characteristics
    9. 5.9 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
        1. 7.3.1.1 TXD
        2. 7.3.1.2 GND
        3. 7.3.1.3 VCC
        4. 7.3.1.4 RXD
        5. 7.3.1.5 VIO
        6. 7.3.1.6 CANH and CANL
        7. 7.3.1.7 S (Silent)
      2. 7.3.2 CAN Bus States
      3. 7.3.3 TXD Dominant Timeout (DTO)
      4. 7.3.4 CAN Bus short-circuit current limiting
      5. 7.3.5 Thermal Shutdown (TSD)
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Unpowered Device
      8. 7.3.8 Floating pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Normal Mode
      3. 7.4.3 Silent Mode
      4. 7.4.4 Driver and Receiver Function
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 CAN Termination
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Bus Loading, Length and Number of Nodes
      3. 8.2.3 Application Curves
      4. 8.2.4 System Examples
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Switching Characteristics

Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Device Switching Characteristics
tPROP(LOOP1) Total loop delay
Driver input (TXD) to receiver output (RXD), recessive to dominant		 S = 0 V, VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 6-4 		125 210 ns
tPROP(LOOP1) Total loop delay
Driver input (TXD) to receiver output (RXD), recessive to dominant		 S = 0 V, VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 6-4 		165 255 ns
tPROP(LOOP2) Total loop delay
Driver input (TXD) to receiver output (RXD), dominant to recessive		 S = 0 V, VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 6-4 		150 210 ns
tPROP(LOOP2) Total loop delay
Driver input (TXD) to receiver output (RXD), dominant to recessive		 S = 0 V, VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 6-4 		180 255 ns
tMODE Mode change time, from normal to standby or from standby to normal See Figure 6-5 20 µs
Driver Switching Characteristics
tpHR Propagation delay time, high TXD to driver recessive (dominant to recessive) S = 0 V
RL = 60 Ω, CL = 100 pF;
See Figure 6-2 		80 ns
tpLD Propagation delay time, low TXD to driver dominant (recessive to dominant) 70 ns
tsk(p) Pulse skew (|tpHR - tpLD|) 14 ns
tR Differential output signal rise time 25 ns
tF Differential output signal fall time 50 ns
tTXD_DTO Dominant timeout S = 0 V
RL = 60 Ω, CL = 100 pF;
See Figure 6-6 		1.2 4.0 ms
Receiver Switching Characteristics
tpRH Propagation delay time, bus recessive input to high output (dominant to recessive) S = 0 V
CL(RXD) = 15 pF;
See Figure 6-3 		81 ns
tpDL Propagation delay time, bus dominant input to low output (recessive to dominant) 66 ns
tR RXD output signal rise time 10 ns
tF RXD output signal fall time 10 ns
FD Timing Characteristics
tBIT(BUS) Bit time on CAN bus output pins
tBIT(TXD) = 500 ns		 S = 0 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS) ;
See Figure 6-4 		450 525 ns
Bit time on CAN bus output pins
tBIT(TXD) = 200 ns		 160 205 ns
Bit time on CAN bus output pins
tBIT(TXD) = 125 ns(1) 		85 130 ns
tBIT(RXD) Bit time on RXD output pins
tBIT(TXD) = 500 ns		 410 540 ns
Bit time on RXD output pins
tBIT(TXD) = 200 ns		 130 210 ns
Bit time on RXD output pins
tBIT(TXD) = 125 ns(1) 		75 135 ns
ΔtREC Receiver timing symmetry
tBIT(TXD) = 500 ns		 -50 20 ns
Receiver timing symmetry
tBIT(TXD) = 200 ns		 -40 10 ns
Receiver timing symmetry
tBIT(TXD) = 125 ns(1) 		-40 10 ns
(1) Measured during characterization and not an ISO 11898-2:2016 parameter.