SLLSF80B
October 2019 – March 2022
TCAN1144-Q1
,
TCAN1145-Q1
,
TCAN1146-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description continued
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
ESD Ratings
8.4
Recommended Operating Conditions
8.5
Thermal Information
8.6
Supply Characteristics
8.7
Electrical Characteristics
8.8
Timing Requirements
8.9
Switching Characteristics
8.10
Typical Characteristics
9
Parameter Measurement Information
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
VSUP Pin
10.3.2
VIO Pin
10.3.3
VCC Pin
10.3.4
GND
10.3.5
INH/LIMP Pin
10.3.6
WAKE Pin
10.3.7
TXD Pin
10.3.8
RXD Pin
10.3.9
SDO/nINT Interrupt Pin
10.3.10
nCS Pin
10.3.11
SCLK
10.3.12
SDI
10.3.13
CANH and CANL Bus Pins
10.4
Device Functional Modes
10.4.1
Normal Mode
10.4.2
Standby Mode
10.4.3
Listen Only Mode
10.4.4
Sleep Mode
10.4.4.1
Bus Wake via RXD Request (BWRR) in Sleep Mode
10.4.4.2
Local Wake Up (LWU) via WAKE Input Terminal
10.4.5
Selective Wake-up
10.4.5.1
Selective Wake Mode (TCAN1145-Q1 and TCAN1146-Q1)
10.4.5.2
Frame Detection (TCAN1145-Q1 and TCAN1146-Q1)
10.4.5.3
Wake-Up Frame (WUF) Validation (TCAN1145-Q1 and TCAN1146-Q1)
10.4.5.4
WUF ID Validation (TCAN1145-Q1 and TCAN1146-Q1)
10.4.5.5
WUF DLC Validation (TCAN1145-Q1 and TCAN1146-Q1)
10.4.5.6
WUF Data Validation (TCAN1145-Q1 and TCAN1146-Q1)
10.4.5.7
Frame error counter (TCAN1145-Q1 and TCAN1146-Q1)
10.4.5.8
CAN FD Frame Tolerance (TCAN1145-Q1 and TCAN1146-Q1)
10.4.6
Fail-safe Features
10.4.6.1
Sleep Mode via Sleep Wake Error
10.4.6.2
Fail-safe Mode
10.4.7
Protection Features
10.4.7.1
Driver and Receiver Function
10.4.7.2
Floating Terminals
10.4.7.3
TXD Dominant Time Out (DTO)
10.4.7.4
CAN Bus Short Circuit Current Limiting
10.4.7.5
Thermal Shutdown
10.4.7.6
Under-Voltage Lockout (UVLO) and Unpowered Device
10.4.7.6.1
UVSUP, UVCC
10.4.7.6.2
UVIO
10.4.7.6.2.1
Fault Behavior
10.4.7.7
Watchdog (TCAN1144-Q1 and TCAN1146-Q1)
10.4.7.7.1
Watchdog Error Counter
10.4.7.7.2
Watchdog SPI Control Programming
10.4.7.7.3
Watchdog Timing
10.4.7.7.4
Question and Answer Watchdog
10.4.7.7.4.1
WD Question and Answer Basic information
10.4.7.7.4.2
Question and Answer Register and Settings
10.4.7.7.4.3
WD Question and Answer Value Generation
10.4.7.7.5
Question and Answer WD Example
10.4.7.7.5.1
Example configuration for desired behavior
10.4.7.7.5.2
Example of performing a question and answer sequence
10.4.8
Bus Fault Detection and Communication (TCAN1144-Q1 and TCAN1146-Q1)
10.4.9
SPI Communication
10.4.9.1
Chip Select Not (nCS):
10.4.9.2
SPI Clock Input (SCLK):
10.4.9.3
SPI Serial Data Input (SDI):
10.4.9.4
SPI Serial Data Output (SDO):
10.5
Programming
10.6
Register Maps
10.6.1
DEVICE_ID_y Register (Address = 0h + formula) [reset = value]
10.6.2
REV_ID_MAJOR Register (Address = 8h) [reset = 01h]
10.6.3
REV_ID_MINOR Register (Address = 9h) [reset = 00h]
10.6.4
SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
10.6.5
Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
10.6.6
MODE_CNTRL Register (Address = 10h) [reset = 04h]
10.6.7
WAKE_PIN_CONFIG Register (Address = 11h) [reset = 4h]
10.6.8
PIN_CONFIG Register (Address = 12h) [reset = 00h]
10.6.9
WD_CONFIG_1 Register (Address = 13h) [reset = 15h]
10.6.10
WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
10.6.11
WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
10.6.12
WD_RST_PULSE Register (Address = 16h) [reset = 07h]
10.6.13
FSM_CONFIG Register (Address = 17h) [reset = 00h]
10.6.14
FSM_CNTR Register (Address = 18h) [reset = 00h]
10.6.15
DEVICE_RST Register (Address = 19h) [reset = 00h]
10.6.16
DEVICE_CONFIG1 Register (Address = 1Ah) [reset = 00h]
10.6.17
DEVICE_CONFIG2 Register (Address = 1Bh) [reset = 0h]
10.6.18
SWE_DIS Register (Address 1Ch) [reset = 04h]
10.6.19
SDO_CONFIG Register (Address = 29h) [reset = 00h]
10.6.20
WD_QA_CONFIG Register (Address = 2Dh) [reset = 00h]
10.6.21
WD_QA_ANSWER Register (Address = 2Eh) [reset = 00h]
10.6.22
WD_QA_QUESTION Register (Address = 2Fh) [reset = 00h]
10.6.23
SW_ID1 Register (Address = 30h) [reset = 00h]
10.6.24
SW_ID2 Register (Address = 31h) [reset = 00h]
10.6.25
SW_ID3 Register (Address = 32h) [reset = 00h]
10.6.26
SW_ID4 Register (Address = 33h) [reset = 00h]
10.6.27
SW_ID_MASK1 Register (Address = 34h) [reset = 00h]
10.6.28
SW_ID_MASK2 Register (Address = 35h) [reset = 00h]
10.6.29
SW_ID_MASK3 Register (Address = 36h) [reset = 00h]
10.6.30
SW_ID_MASK4 Register (Address = 37h) [reset = 00h]
10.6.31
SW_ID_MASK_DLC Register (Address = 38h) [reset = 00h]
10.6.32
DATA_y Register (Address = 39h + formula) [reset = 00h]
10.6.33
SW_RSVD_y Register (Address = 41h + formula) [reset = 00h]
10.6.34
SW_CONFIG_1 Register (Address = 44h) [reset = 50h]
10.6.35
SW_CONFIG_2 Register (Address = 45h) [reset = 00h]
10.6.36
SW_CONFIG_3 Register (Address = 46h) [reset = 1Fh]
10.6.37
SW_CONFIG_4 Register (Address = 47h) [reset = 00h]
10.6.38
SW_CONFIG_RSVD_y Register (Address = 48h + formula) [reset = 00h]
10.6.39
INT_GLOBAL Register (Address = 50h) [reset = 00h]
10.6.40
INT_1 Register (Address = 51h) [reset = 00h]
10.6.41
INT_2 Register (Address = 52h) [reset = 40h]
10.6.42
INT_3 Register (Address 53h) [reset = 00h]
10.6.43
INT_CANBUS Register (Address = 54h) [reset = 00h]
10.6.44
INT_GLOBAL_ENABLE (Address = 55h) [reset = 00h]
10.6.45
INT_ENABLE_1 Register (Address = 56h) [reset = FFh]
10.6.46
INT_ENABLE_2 Register (Address = 57h) [reset = 1Fh]
10.6.47
INT_ENABLE_3 Register (Address = 58h) [reset = 0h]
10.6.48
INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
10.6.49
INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
11
Application Information Disclaimer
11.1
Application Information
11.1.1
BUS Loading, Length and Number of Nodes
11.1.2
CAN Termination
11.1.2.1
Termination
11.1.2.2
CAN Bus Biasing
11.2
Typical Application
11.2.1
Design Requirements
11.2.2
Detailed Design Procedure
11.2.2.1
Brownout
11.2.3
Application Curves
12
Power Supply Recommendations
13
Layout
13.1
Layout Guidelines
13.2
Layout Example
14
Device and Documentation Support
14.1
Documentation Support
14.1.1
CAN Transceiver Physical Layer Standards:
14.1.2
EMC Requirements:
14.1.3
Conformance Test Requirements:
14.1.4
Related Documentation
14.2
Receiving Notification of Documentation Updates
14.3
Support Resources
14.4
Trademarks
14.5
Electrostatic Discharge Caution
14.6
Glossary
15
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DYY|14
MPSS114B
DMT|14
MPSS087B
D|14
MPDS177G
Thermal pad, mechanical data (Package|Pins)
DMT|14
QFND638
D|14
QFND304D
Orderable Information
sllsf80b_oa
sllsf80b_pm
8
Specifications