SLLSF31A May   2021  – December 2021 TCAN1162-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings IEC Specification
    4. 7.4 Recomended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Power Supply Characteristics
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VSUP Pin
      2. 9.3.2  VFLT Pin
      3. 9.3.3  Digital Inputs and Outputs
        1. 9.3.3.1 TXD Pin
        2. 9.3.3.2 RXD Pin
        3. 9.3.3.3 TS Pin
      4. 9.3.4  Digital Control and Timing
      5. 9.3.5  VIO Pin
      6. 9.3.6  GND
      7. 9.3.7  INH Pin
      8. 9.3.8  WAKE Pin
      9. 9.3.9  CAN Bus Pins
      10. 9.3.10 Local Faults
        1. 9.3.10.1 TXD Dominant Timeout (TXD DTO)
        2. 9.3.10.2 Thermal Shutdown (TSD)
        3. 9.3.10.3 Under/Over Voltage Lockout
        4. 9.3.10.4 Unpowered Devices
        5. 9.3.10.5 Floating Terminals
        6. 9.3.10.6 CAN Bus Short Circuit Current Limiting
        7. 9.3.10.7 Sleep Wake Error Timer
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Mode Description
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Standby Mode
        3. 9.4.1.3 Sleep Mode
          1. 9.4.1.3.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 9.4.1.3.2 Local Wake-Up (LWU) via WAKE Input Terminal
        4. 9.4.1.4 Fail-safe Mode
      2. 9.4.2 CAN Transceiver
        1. 9.4.2.1 CAN Transceiver Operation
        2. 9.4.2.2 CAN Transceiver Modes
          1. 9.4.2.2.1 CAN Off Mode
          2. 9.4.2.2.2 CAN Autonomous: Inactive and Active
          3. 9.4.2.2.3 CAN Active
        3. 9.4.2.3 Driver and Receiver Function Tables
        4. 9.4.2.4 CAN Bus States
  10. 10Application Information
    1. 10.1 Application Information Disclaimer
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Termination
    3. 10.3 Application Curves
  11. 11Power Supply Requirements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Electrical Characteristics

Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CAN Driver Electrical Characteristics
VO(D) Dominant output voltage
Bus biasing active		 CANH TXD = 0 V, 50 ≤ RL ≤ 65 Ω, CL = open, RCM = open
See Figure 8-2		 2.75 4.5 V
Dominant output voltage
Bus biasing active		 CANL 0.5 2.25 V
VO(R) Recessive output voltage
Bus biasing active		 TXD = VIO, RL = open (no load), RCM = open
See Figure 8-2		 2 3 V
VSYM Driver symmetry
Bus biasing active

(VO(CANH) + VO(CANL) ) / VFLT
 nSLP = VIO, RL = 60 Ω, CSPLIT = 4.7 nF, CL = Open, RCM = Open, TXD = 250 kHz, 1 Mhz, 2.5 MHz
See Figure 8-2		 0.9 1.1 V/V
VSYM_DC DC Driver symmetry
Bus biasing active

VFLT – VO(CANH) – VO(CANL)
 nSLP = VIO, RL = 60 Ω, CL = open
See Figure 8-2		 –400 400 mV
VOD(DOM) Differential output voltage
Bus biasing active
Dominant		 CANH - CANL nSLP = VIO, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
See Figure 8-2		 1.5 3 V
Differential output voltage
Bus biasing active
Dominant		 CANH - CANL nSLP = VIO, TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open
See Figure 8-2		 1.4 3.3 V
Differential output voltage
Bus biasing active
Dominant		 CANH - CANL nSLP = VIO, TXD = 0 V, RL = 2240 Ω, CL = open
See Figure 8-2		 1.5 5 V
VOD(REC) Differential output voltage
Bus biasing active
Bus biasing inactive
Recessive		 CANH - CANL nSLP = VIO, TXD = VIO, RL = open Ω, CL = open
See Figure 8-2		 –50 50 mV
VO(INACT) Pin output voltage
Bus biasing inactive		 CANH nSLP = 0 V, TXD = VIO
RL = open (no load), CL = open
See Figure 8-2		 -0.1 0.1 V
CANL nSLP = 0 V, TXD = VIO
RL = open (no load), CL = open
See Figure 8-2		 -0.1 0.1 V
VOD(STB) Differential output voltage
Bus biasing inactive		 CANH - CANL nSLP = 0 V, TXD = VIO
RL = open (no load), CL = open
See Figure 8-2		 -0.2 0.2 V
IOS(DOM) Short-circuit steady-state output current
Bus biasing active
Dominant		 nSLP = VIO, TXD = 0 V
-15 V ≤ V(CANH) ≤ 40 V
See Figure 8-2 and Figure 8-6		 –75 mA
Short-circuit steady-state output current
Bus biasing active
Dominant		 nSLP = VIO, TXD = 0 V
-15 V ≤ V(CANL) ≤ 40 V
See Figure 8-2 and Figure 8-6		 75 mA
IOS(REC) Short-circuit steady-state output current
Bus biasing active
Recessive		 nSLP = VIO, VBUS = CANH = CANL
-27 V ≤ VBUS ≤ 42 V
See Figure 8-2 and Figure 8-6		 –3 3 mA
CAN Receiver Electrical Characteristics
VIT(DOM) Receiver dominant state input voltage range
Bus biasing active		 nSLP = VIO, -12 V ≤ VCM ≤ 12 V
See Figure 8-3 and Table 9-4		 0.9 8 V
VIT(REC) Receiver recessive state input voltage range
Bus biasing active		 -3 0.5 V
VHYS Hysteresis voltage for input threshold
Bus biasing active		 nSLP = VIO
See Figure 8-3 and Table 9-4		 80 140 mV
VDIFF(MAX) Maximum rating of VDIFF -5 10 V
VDIFF(DOM) Receiver dominant state input voltage range
Bus biasing inactive		 nSLP = 0 V, -12 V ≤ VCM ≤ 12 V
See Figure 8-3 and Table 9-4		 1.150 8 V
VDIFF(REC) Receiver recessive state input voltage range
Bus biasing inactive		 -3 0.4 V
VCM Common mode range nSLP = VIO
See Figure 8-3 and Table 9-4		 –12 12 V
IOFF(LKG) Power-off (unpowered) bus input leakage current VSUP = 0 V, CANH = CANL = 5 V 2.5 µA
CI Input capacitance to ground (CANH or CANL)(1) TXD = VIO 20 pF
CID Differential input capacitance(1) TXD = VIO 10 pF
RID Differential input resistance TXD = VIO, nSLP = 5 V
-12 V ≤ VCM ≤ 12 V		 50 100 kΩ
RIN Input resistance (CANH or CANL) 25 50 kΩ
RIN(M) Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%		 V(CANH) = V(CANL) = 5 V –1 1 %
TXD Input Characteristics
VIH High level input voltage 0.7 VIO
VIL Low level input voltage 0.3 VIO
IIH High level input leakage current TXD = VIO = 5.5 V –1 0 1 µA
IIL Low level input leakage current TXD = 0 V, VIO = 5.5 V –130 –15 µA
RPU Pull-up resistance 40 60 80 kΩ
ILKG(OFF) Unpowered leakage current TXD = 5.5 V, VSUP = VIO = 0 V –1 0 1 µA
CI Input Capacitance VIN = 0.4 x sin(2 × π × 2 × 106 × t) + 2.5 V 5 pF
RXD Output Characteristics
VOH High level output voltage IO = –2 mA. 0.8 VIO
VOL Low level output voltage IO = 2 mA. 0.2 VIO
RPU Pull-up resistance 40 60 80 kΩ
ILKG(OFF) Unpowered leakage curret RXD = 5.5 V, VSUP = VIO = 0 V -5 5 µA
nSLP Input Characteristics
VIH High level input voltage 0.7 VIO
VIL Low level input voltage 0.3 VIO
IIH High level input leakage current nSLP = VIO = 5.5 V 50 130 µA
IIL Low level input leakage current nSLP = 0 V, VIO = 5.5 V –1 1 µA
RPD Pull-down resistance 40 60 80 kΩ
ILKG(OFF) Unpowered leakage current nSLP = 5.5 V, VIO = 0 V –1 0 1 µA
INH Output Characteristics
ΔVH High level voltage drop INH with respect to VSUP IINH = –6 mA 0.5 1 V
ILKG(INH) Sleep mode leakage current INH = 0 V –0.5 0.5 µA
WAKE Input Characteristics
VIH High-level input voltage Sleep mode 4 V
VIL Low-level input voltage 2 V
IIL Low level input leakage current WAKE = 1 V 3 µA
VHYS Input hysteresis 800 1200 mV
IIH High level input leakage current –1 0 1 µA
TS Output Characteristics
VOH High-level output voltage IO = -2 mA 0.8 VIO
VOL Low-level output voltage IO = 2 mA 0.2 VIO
ILKG(OFF) Unpowered leakage current TS = 5.5 V, VIO = 0 V –1 0 1 µA
(1) Test according to ISO 11898-2:2003