SLLSF83A May 2021 – November 2021 TCAN11623-Q1 , TCAN11625-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
CAN Driver Electrical Characteristics | |||||||
VO(D) | Dominant output voltage Bus biasing active |
CANH | TXD = 0 V, 50 ≤ RL ≤ 65 Ω, CL = open, RCM = open See Figure 9-2 |
2.75 | 4.5 | V | |
Dominant output voltage Bus biasing active |
CANL | 0.5 | 2.25 | V | |||
VO(R) | Recessive output voltage Bus biasing active |
TXD = VIO, RL = open (no load), RCM = open See Figure 9-2 |
2 | 3 | V | ||
VSYM | Driver symmetry Bus biasing active (VO(CANH) + VO(CANL) ) / VCCOUT (VO(CANH) + VO(CANL) ) / VFLT |
nSLP = VIO, RL = 60 Ω, CSPLIT = 4.7 nF, CL = Open, RCM = Open, TXD = 250 kHz, 1 Mhz, 2.5 MHz See Figure 9-2 |
0.9 | 1.1 | V/V | ||
VSYM_DC | DC Driver symmetry Bus biasing active VCCOUT – VO(CANH) – VO(CANL) VFLT – VO(CANH) – VO(CANL) |
nSLP = VIO, RL = 60 Ω, CL = open See Figure 9-2 |
–400 | 400 | mV | ||
VOD(DOM) | Differential output voltage Bus biasing active Dominant |
CANH - CANL | nSLP = VIO, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open See Figure 9-2 |
1.5 | 3 | V | |
Differential output voltage Bus biasing active Dominant |
CANH - CANL | nSLP = VIO, TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open See Figure 9-2 |
1.4 | 3.3 | V | ||
Differential output voltage Bus biasing active Dominant |
CANH - CANL | nSLP = VIO, TXD = 0 V, RL = 2240 Ω, CL = open See Figure 9-2 |
1.5 | 5 | V | ||
VOD(REC) | Differential output voltage Bus biasing active Bus biasing inactive Recessive |
CANH - CANL | nSLP = VIO, TXD = VIO, RL = open Ω, CL = open See Figure 9-2 |
–50 | 50 | mV | |
VO(INACT) | Pin output voltage Bus biasing inactive |
CANH | nSLP = 0 V, TXD = VIO RL = open (no load), CL = open See Figure 9-2 |
-0.1 | 0.1 | V | |
CANL | nSLP = 0 V, TXD = VIO RL = open (no load), CL = open See Figure 9-2 |
-0.1 | 0.1 | V | |||
VOD(STB) | Differential output voltage Bus biasing inactive |
CANH - CANL | nSLP = 0 V, TXD = VIO RL = open (no load), CL = open See Figure 9-2 |
-0.2 | 0.2 | V | |
IOS(DOM) | Short-circuit steady-state output current Bus biasing active Dominant |
nSLP = VIO, TXD = 0 V -15 V ≤ V(CANH) ≤ 40 V See Figure 9-2 and Figure 9-8 |
–75 | mA | |||
Short-circuit steady-state output current Bus biasing active Dominant |
nSLP = VIO, TXD = 0 V -15 V ≤ V(CANL) ≤ 40 V See Figure 9-2 and Figure 9-8 |
75 | mA | ||||
IOS(REC) | Short-circuit steady-state output current Bus biasing active Recessive |
nSLP = VIO, VBUS = CANH = CANL -27 V ≤ VBUS ≤ 42 V See Figure 9-2 and Figure 9-8 |
–3 | 3 | mA | ||
CAN Receiver Electrical Characteristics | |||||||
VIT(DOM) | Receiver dominant state input voltage range Bus biasing active |
nSLP = VIO, -12 V ≤ VCM ≤ 12 V See Figure 9-3 and Table 10-6 |
0.9 | 8 | V | ||
VIT(REC) | Receiver recessive state input voltage range Bus biasing active |
-3 | 0.5 | V | |||
VHYS | Hysteresis voltage for input threshold Bus biasing active |
nSLP = VIO See Figure 9-3 and Table 10-6 |
80 | 140 | mV | ||
VDIFF(MAX) | Maximum rating of VDIFF | -5 | 10 | V | |||
VDIFF(DOM) | Receiver dominant state input voltage range Bus biasing inactive |
nSLP = 0 V, -12 V ≤ VCM ≤ 12 V See Figure 9-3 and Table 10-6 |
1.150 | 8 | V | ||
VDIFF(REC) | Receiver recessive state input voltage range Bus biasing inactive |
-3 | 0.4 | V | |||
VCM | Common mode range | nSLP = VIO See Figure 9-3 and Table 10-6 |
–12 | 12 | V | ||
IOFF(LKG) | Power-off (unpowered) bus input leakage current | VSUP = 0 V, CANH = CANL = 5 V | 2.5 | µA | |||
CI | Input capacitance to ground (CANH or CANL)(1) | TXD = VIO | 20 | pF | |||
CID | Differential input capacitance(1) | TXD = VIO | 10 | pF | |||
RID | Differential input resistance | TXD = VIO, nSLP = 5 V -12 V ≤ VCM ≤ 12 V |
50 | 100 | kΩ | ||
RIN | Input resistance (CANH or CANL) | 25 | 50 | kΩ | |||
RIN(M) | Input resistance matching: [1 – RIN(CANH) / RIN(CANL)] × 100% |
V(CANH) = V(CANL) = 5 V | –1 | 1 | % | ||
TXD Input Characteristics | |||||||
VIH | High level input voltage | 0.7 | VIO | ||||
VIL | Low level input voltage | 0.3 | VIO | ||||
IIH | High level input leakage current | TXD = VIO = 5.5 V | –1 | 0 | 1 | µA | |
IIL | Low level input leakage current | TXD = 0 V, VIO = 5.5 V | –130 | –15 | µA | ||
RPU | Pull-up resistance | 40 | 60 | 80 | kΩ | ||
ILKG(OFF) | Unpowered leakage current | TXD = 5.5 V, VSUP = VIO = 0 V | –1 | 0 | 1 | µA | |
CI | Input Capacitance | VIN = 0.4 x sin(2 × π × 2 × 106 × t) + 2.5 V | 5 | pF | |||
RXD Output Characteristics | |||||||
VOH | High level output voltage | IO = –2 mA. | 0.8 | VIO | |||
VOL | Low level output voltage | IO = 2 mA. | 0.2 | VIO | |||
RPU | Pull-up resistance | 40 | 60 | 80 | kΩ | ||
ILKG(OFF) | Unpowered leakage curret | RXD = 5.5 V, VSUP = VIO = 0 V | -5 | 5 | µA | ||
nSLP Input Characteristics | |||||||
VIH | High level input voltage | 0.7 | VIO | ||||
VIL | Low level input voltage | 0.3 | VIO | ||||
IIH | High level input leakage current | nSLP = VIO = 5.5 V | 50 | 130 | µA | ||
IIL | Low level input leakage current | nSLP = 0 V, VIO = 5.5 V | –1 | 1 | µA | ||
RPD | Pull-down resistance | 40 | 60 | 80 | kΩ | ||
ILKG(OFF) | Unpowered leakage current | nSLP = 5.5 V, VIO = 0 V | –1 | 0 | 1 | µA | |
INH Output Characteristics | |||||||
ΔVH | High level voltage drop INH with respect to VSUP | IINH = –6 mA | 0.5 | 1 | V | ||
ILKG(INH) | Sleep mode leakage current | INH = 0 V | –0.5 | 0.5 | µA | ||
WAKE Input Characteristics | |||||||
VIH | High-level input voltage | Sleep mode | 4 | V | |||
VIL | Low-level input voltage | 2 | V | ||||
IIL | Low level input leakage current | WAKE = 1 V | 3 | µA | |||
VHYS | Input hysteresis | 800 | 1200 | mV | |||
nRST Bidirectional Characteristics | |||||||
VIH | High level input voltage | 0.8 | VCCOUT | ||||
VIL | Low level input voltage | 0.2 | VCCOUT | ||||
VIH | High level input voltage | 0.8 | VLDO3 | ||||
VIL | Low level input voltage | 0.2 | VLDO3 | ||||
VOL | Low level output voltage (TCAN11625) | IO = 2 mA. | 0.2 | VCCOUT | |||
VOL | Low level output voltage (TCAN11623) | IO = 2 mA. | 0.2 | VLDO3 | |||
IIH | High level input leakage current | –1 | 0 | 1 | µA | ||
RPU | Pull-up resistance to VLDO | 160 | 240 | 320 | kΩ | ||
TS Output Characteristics | |||||||
VOH | High-level output voltage | IO = -2 mA | 0.8 | VIO | |||
VOL | Low-level output voltage | IO = 2 mA | 0.2 | VIO | |||
ILKG(OFF) | Unpowered leakage current | TS = 5.5 V, VIO = 0 V | –1 | 0 | 1 | µA |