SLLSFE3 December   2021 TCAN1164-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configurations and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 ESD Ratings IEC Specification
    4. 8.4 Recomended Operating Conditions
    5. 8.5 Thermal Information
    6. 8.6 Power Supply Characteristics
    7. 8.7 Electrical Characteristics
    8. 8.8 Switching Characteristics
    9. 8.9 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  VSUP Pin
      2. 10.3.2  VCCOUT Pin
      3. 10.3.3  Digital Inputs and Outputs
        1. 10.3.3.1 TXD Pin
        2. 10.3.3.2 RXD Pin
      4. 10.3.4  GND
      5. 10.3.5  nRST Pin
      6. 10.3.6  SDO
      7. 10.3.7  nCS Pin
      8. 10.3.8  SCLK
      9. 10.3.9  SDI
      10. 10.3.10 CAN Bus Pins
      11. 10.3.11 Local Faults
        1. 10.3.11.1 TXD Dominant Timeout (TXD DTO)
        2. 10.3.11.2 Thermal Shutdown (TSD)
        3. 10.3.11.3 Under/Over Voltage Lockout
        4. 10.3.11.4 Unpowered Devices
        5. 10.3.11.5 Floating Terminals
        6. 10.3.11.6 CAN Bus Short Circuit Current Limiting
        7. 10.3.11.7 Sleep Wake Error Timer
      12. 10.3.12 Watchdog
        1. 10.3.12.1 Watchdog Error Counter
        2. 10.3.12.2 Watchdog SPI Control Programming
        3. 10.3.12.3 Watchdog Timing
        4. 10.3.12.4 Question and Answer Watchdog
          1. 10.3.12.4.1 WD Question and Answer Basic information
          2. 10.3.12.4.2 Question and Answer Register and Settings
          3. 10.3.12.4.3 WD Question and Answer Value Generation
        5. 10.3.12.5 Question and Answer WD Example
          1. 10.3.12.5.1 Example configuration for desired behavior
          2. 10.3.12.5.2 Example of performing a question and answer sequence
      13. 10.3.13 Bus Fault Detection and Communication
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operating Mode Description
        1. 10.4.1.1 Normal Mode
        2. 10.4.1.2 Silent Mode
        3. 10.4.1.3 Standby Mode
          1. 10.4.1.3.1 Wake-Up Pattern (WUP) Detection in Standby Mode
        4. 10.4.1.4 Reset Mode
        5. 10.4.1.5 Fail-safe Mode
      2. 10.4.2 CAN Transceiver
        1. 10.4.2.1 CAN Transceiver Operation
        2. 10.4.2.2 CAN Transceiver Modes
          1. 10.4.2.2.1 CAN Off Mode
          2. 10.4.2.2.2 CAN Autonomous: Inactive and Active
          3. 10.4.2.2.3 CAN Active
        3. 10.4.2.3 Driver and Receiver Function Tables
        4. 10.4.2.4 CAN Bus States
    5. 10.5 Programming
      1. 10.5.1 Serial Peripheral Interface (SPI) Communication
      2. 10.5.2 Serial Clock Input (SCLK)
      3. 10.5.3 Serial Data Input (SDI)
      4. 10.5.4 Serial Data Output (SDO)
      5. 10.5.5 Chip Select Not (nCS)
      6. 10.5.6 Registers
        1. 10.5.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = xxh]
        2. 10.5.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 00h]
        3. 10.5.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 00h]
        4. 10.5.6.4  SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
        5. 10.5.6.5  Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
        6. 10.5.6.6  MODE_CNTRL Register (Address = 10h) [reset = 04h]
        7. 10.5.6.7  WD_CONFIG_1 Register (Address = 13h) [reset = 54h]
        8. 10.5.6.8  WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
        9. 10.5.6.9  WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
        10. 10.5.6.10 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0h]
        11. 10.5.6.11 WD_QA_ANSWER Register (Address = 2Eh) [reset = 0h]
        12. 10.5.6.12 WD_QA_QUESTION Register (Address = 2Fh) [reset = 0h]
        13. 10.5.6.13 STATUS (address = 40h) [reset = 00h]
        14. 10.5.6.14 INT_GLOBAL Register (Address = 50h) [reset = 0h]
        15. 10.5.6.15 INT_1 Register (Address = 51h) [reset = 0h]
        16. 10.5.6.16 INT_2 Register (Address = 52h) [reset = 40h]
        17. 10.5.6.17 INT_3 Register (Address 53h) [reset = 0h]
        18. 10.5.6.18 INT_CANBUS Register (Address = 54h) [reset = 0h]
        19. 10.5.6.19 INT_ENABLE_1 Register (Address = 56h) [reset = F3h]
        20. 10.5.6.20 INT_ENABLE_2 Register (Address = 57h) [reset = 3Fh]
        21. 10.5.6.21 INT_ENABLE_3 Register (Address =58h) [reset = 80h]
        22. 10.5.6.22 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
        23. 10.5.6.23 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
  11. 11Application Information Disclaimer
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Bus Loading, Length and Number of Nodes
      2. 11.2.2 Detailed Design Procedures
        1. 11.2.2.1 CAN Termination
    3. 11.3 Application Curves
  12. 12Power Supply Requirements
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 Support Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3.13 Bus Fault Detection and Communication

The TCAN1164-Q1 provides advanced bus fault detection. TCAN1164-Q1 is used for illustration purposes. The device can determine certain fault conditions and set a status/interrupt flag so that the MCU can understand what the fault is. Detection takes place and is recorded if the fault is present during four dominant to recessive transitions with each dominant bit being ≥ 2 µs. As with any bus architecture where termination resistors are at each end not every fault can be specified to the lowest level, meaning exact location. The fault detection circuitry is monitoring the CANH and CANL pins (currents) to determine if there is a short to battery, short to ground, short to each other or opens. From a system perspective, the location of the device can impact what fault can be detected. See Figure 10-8 as an example of node locations and how they can impact the ability to determine the actual fault location. Figure 10-9 through Figure 10-13 show the various bus faults based upon the three node configuration. Table 10-10 shows what can be detected and by which device. Fault 1 is detected as ½ termination and Fault 2 is detected as no termination.

Bus fault detection is a system-level situation. If the fault is occurring at the ECU then the general communication of the bus is compromised. For complete coverage of a node a system level diagnostic step for each node and the ability to communicate this back to a central point is needed.

Figure 10-8 Three Node Example
Figure 10-9 Fault 1 and 2 Examples
Figure 10-10 Fault 3 and 4 Examples
Figure 10-11 Fault 5 and 6 Examples
Figure 10-12 Fault 7, 8 and 9 Examples
Figure 10-13 Fault 10 and 11 Examples
Table 10-10 Bus Fault Pin State and Detection Table
Fault #CANHCANLFault Detected
1OpenOpenAll positions see this fault as half termination and detect them
2OpenOpenDepending upon open location the device detects this as no termination.
3OpenNormalYes but cannot tell the difference between it and Fault 2 and 4; Device 2 and Device 3 does not see this fault
4NormalOpenYes but cannot tell the difference between it and Fault 2 and 3; Device 2 and Device 3 does not see this fault
5Shorted to CANLShorted to CANHYes but not location
6Shorted to VbatNormalYes but not location
7Shorted to GNDNormalYes but cannot tell the difference between this and Fault 10
8NormalShorted to VbatYes but cannot tell the difference between this and Fault 11
9NormalShorted to GNDYes but not location
10Shorted to GNDShorted to GNDYes but cannot tell the difference between this and Fault 7
11Shorted to VbatShorted to VbatYes but cannot tell the difference between this and Fault 8
Table 10-11 Bus Fault Interrupt Flags Mapping to Fault Detection Number
AddressBIT(S)DEFAULTFLAGDESCRIPTIONFAULT DETECTEDACCESS
8'h5471'b0RSVDReserved
61'b0CANBUSTERMOPENCAN Bus has one termination point openFault 1R/WC
51'b0CANHCANLCANH and CANL Shorted TogetherFault 5R/WC
41'b0CANHBATCANH Shorted to VbatFault 6R/WC
31'b0CANLGNDCANL Shorted to GNDFault 9R/WC
21'b0CANBUSOPENCAN Bus Open (One of three possible places)Faults 2, 3 and 4R/WC
11'b0CANBUSGNDCANH Shorted to GND or Both CANH & CANL Shorted to GNDFaults 7 and 10R/WC
01'b0CANBUSBATCANL Shorted to Vbat or Both CANH & CANL Shorted to VbatFaults 8 and 11R/WC