SLLSFE3 December   2021 TCAN1164-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configurations and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 ESD Ratings IEC Specification
    4. 8.4 Recomended Operating Conditions
    5. 8.5 Thermal Information
    6. 8.6 Power Supply Characteristics
    7. 8.7 Electrical Characteristics
    8. 8.8 Switching Characteristics
    9. 8.9 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  VSUP Pin
      2. 10.3.2  VCCOUT Pin
      3. 10.3.3  Digital Inputs and Outputs
        1. 10.3.3.1 TXD Pin
        2. 10.3.3.2 RXD Pin
      4. 10.3.4  GND
      5. 10.3.5  nRST Pin
      6. 10.3.6  SDO
      7. 10.3.7  nCS Pin
      8. 10.3.8  SCLK
      9. 10.3.9  SDI
      10. 10.3.10 CAN Bus Pins
      11. 10.3.11 Local Faults
        1. 10.3.11.1 TXD Dominant Timeout (TXD DTO)
        2. 10.3.11.2 Thermal Shutdown (TSD)
        3. 10.3.11.3 Under/Over Voltage Lockout
        4. 10.3.11.4 Unpowered Devices
        5. 10.3.11.5 Floating Terminals
        6. 10.3.11.6 CAN Bus Short Circuit Current Limiting
        7. 10.3.11.7 Sleep Wake Error Timer
      12. 10.3.12 Watchdog
        1. 10.3.12.1 Watchdog Error Counter
        2. 10.3.12.2 Watchdog SPI Control Programming
        3. 10.3.12.3 Watchdog Timing
        4. 10.3.12.4 Question and Answer Watchdog
          1. 10.3.12.4.1 WD Question and Answer Basic information
          2. 10.3.12.4.2 Question and Answer Register and Settings
          3. 10.3.12.4.3 WD Question and Answer Value Generation
        5. 10.3.12.5 Question and Answer WD Example
          1. 10.3.12.5.1 Example configuration for desired behavior
          2. 10.3.12.5.2 Example of performing a question and answer sequence
      13. 10.3.13 Bus Fault Detection and Communication
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operating Mode Description
        1. 10.4.1.1 Normal Mode
        2. 10.4.1.2 Silent Mode
        3. 10.4.1.3 Standby Mode
          1. 10.4.1.3.1 Wake-Up Pattern (WUP) Detection in Standby Mode
        4. 10.4.1.4 Reset Mode
        5. 10.4.1.5 Fail-safe Mode
      2. 10.4.2 CAN Transceiver
        1. 10.4.2.1 CAN Transceiver Operation
        2. 10.4.2.2 CAN Transceiver Modes
          1. 10.4.2.2.1 CAN Off Mode
          2. 10.4.2.2.2 CAN Autonomous: Inactive and Active
          3. 10.4.2.2.3 CAN Active
        3. 10.4.2.3 Driver and Receiver Function Tables
        4. 10.4.2.4 CAN Bus States
    5. 10.5 Programming
      1. 10.5.1 Serial Peripheral Interface (SPI) Communication
      2. 10.5.2 Serial Clock Input (SCLK)
      3. 10.5.3 Serial Data Input (SDI)
      4. 10.5.4 Serial Data Output (SDO)
      5. 10.5.5 Chip Select Not (nCS)
      6. 10.5.6 Registers
        1. 10.5.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = xxh]
        2. 10.5.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 00h]
        3. 10.5.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 00h]
        4. 10.5.6.4  SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
        5. 10.5.6.5  Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
        6. 10.5.6.6  MODE_CNTRL Register (Address = 10h) [reset = 04h]
        7. 10.5.6.7  WD_CONFIG_1 Register (Address = 13h) [reset = 54h]
        8. 10.5.6.8  WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
        9. 10.5.6.9  WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
        10. 10.5.6.10 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0h]
        11. 10.5.6.11 WD_QA_ANSWER Register (Address = 2Eh) [reset = 0h]
        12. 10.5.6.12 WD_QA_QUESTION Register (Address = 2Fh) [reset = 0h]
        13. 10.5.6.13 STATUS (address = 40h) [reset = 00h]
        14. 10.5.6.14 INT_GLOBAL Register (Address = 50h) [reset = 0h]
        15. 10.5.6.15 INT_1 Register (Address = 51h) [reset = 0h]
        16. 10.5.6.16 INT_2 Register (Address = 52h) [reset = 40h]
        17. 10.5.6.17 INT_3 Register (Address 53h) [reset = 0h]
        18. 10.5.6.18 INT_CANBUS Register (Address = 54h) [reset = 0h]
        19. 10.5.6.19 INT_ENABLE_1 Register (Address = 56h) [reset = F3h]
        20. 10.5.6.20 INT_ENABLE_2 Register (Address = 57h) [reset = 3Fh]
        21. 10.5.6.21 INT_ENABLE_3 Register (Address =58h) [reset = 80h]
        22. 10.5.6.22 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
        23. 10.5.6.23 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
  11. 11Application Information Disclaimer
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Bus Loading, Length and Number of Nodes
      2. 11.2.2 Detailed Design Procedures
        1. 11.2.2.1 CAN Termination
    3. 11.3 Application Curves
  12. 12Power Supply Requirements
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Receiving Notification of Documentation Updates
    3. 14.3 Support Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.4.1.3 Standby Mode

The RXD output pin is asserted low while in standby mode if the a wake event or a fault is detected. Note that a POR counts as a wake event and will also cause RXD to latch low.

In standby mode a fail-safe timer, tINACTIVE, is enabled. The tINACTIVE timer add an additional layer of protection by requiring the system controller to configure the TCAN1164-Q1 to normal mode before it expires. This feature forces the TCAN1164-Q1 to transition to its lowest power mode, standby mode with a SWE interrupt flag set, if the processor does not come up properly.