SLLSFF0 December 2021 TCAN1167-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
This pin is high impedance until the SPI output is enabled via nCS. Once the SPI is enabled by a low on nCS, the SDO is immediately driven high or low showing the global interrupt register 8'h50, bit 7. The Global Interrupt register, INT_GLOBAL, is the first byte to be shifted out. The SDO pin provides data out from the device to the processor. For a write command this is the only data that will be provided on the SDO pin. For a read command he one to three bytes of data from successive address will be provided on the SDO line. Figure 9-24 and Figure 9-25 shows examples of a single address read and of a three sequential address read utilizing the 32-bit burst read. The 32-bit burst read shows the global interrupt register followed by the three requested data bytes.
If a read happens faster than 2 µs after a write the global fault flag status may not reflect any status change that the write may have initiated.