SLLSFF0 December   2021 TCAN1167-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 ESD Ratings IEC Specification
    4. 7.4 Recomended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Power Supply Characteristics
    7. 7.7 Electrical Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VSUP Pin
      2. 9.3.2  VCCOUT Pin
      3. 9.3.3  Digital Inputs and Outputs
        1. 9.3.3.1 TXD Pin
        2. 9.3.3.2 RXD Pin
      4. 9.3.4  GND
      5. 9.3.5  INH Pin
      6. 9.3.6  WAKE Pin
      7. 9.3.7  nRST Pin
      8. 9.3.8  SDO
      9. 9.3.9  nCS Pin
      10. 9.3.10 SCLK
      11. 9.3.11 SDI
      12. 9.3.12 CAN Bus Pins
      13. 9.3.13 Local Faults
        1. 9.3.13.1 TXD Dominant Timeout (TXD DTO)
        2. 9.3.13.2 Thermal Shutdown (TSD)
        3. 9.3.13.3 Under/Over Voltage Lockout
        4. 9.3.13.4 Unpowered Devices
        5. 9.3.13.5 Floating Terminals
        6. 9.3.13.6 CAN Bus Short Circuit Current Limiting
        7. 9.3.13.7 Sleep Wake Error Timer
      14. 9.3.14 Watchdog
        1. 9.3.14.1 Watchdog Error Counter
        2. 9.3.14.2 Watchdog SPI Control Programming
        3. 9.3.14.3 Watchdog Timing
        4. 9.3.14.4 Question and Answer Watchdog
          1. 9.3.14.4.1 WD Question and Answer Basic information
          2. 9.3.14.4.2 Question and Answer Register and Settings
          3. 9.3.14.4.3 WD Question and Answer Value Generation
        5. 9.3.14.5 Question and Answer WD Example
          1. 9.3.14.5.1 Example configuration for desired behavior
          2. 9.3.14.5.2 Example of performing a question and answer sequence
      15. 9.3.15 Bus Fault Detection and Communication
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Mode Description
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Silent Mode
        3. 9.4.1.3 Standby Mode
        4. 9.4.1.4 Sleep Mode
          1. 9.4.1.4.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 9.4.1.4.2 Local Wake-Up (LWU) via WAKE Input Terminal
        5. 9.4.1.5 Reset Mode
        6. 9.4.1.6 Fail-safe Mode
      2. 9.4.2 CAN Transceiver
        1. 9.4.2.1 CAN Transceiver Operation
        2. 9.4.2.2 CAN Transceiver Modes
          1. 9.4.2.2.1 CAN Off Mode
          2. 9.4.2.2.2 CAN Autonomous: Inactive and Active
          3. 9.4.2.2.3 CAN Active
        3. 9.4.2.3 Driver and Receiver Function Tables
        4. 9.4.2.4 CAN Bus States
    5. 9.5 Programming
      1. 9.5.1 Serial Peripheral Interface (SPI) Communication
      2. 9.5.2 Serial Clock Input (SCLK)
      3. 9.5.3 Serial Data Input (SDI)
      4. 9.5.4 Serial Data Output (SDO)
      5. 9.5.5 Chip Select Not (nCS)
      6. 9.5.6 Registers
        1. 9.5.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = xxh]
        2. 9.5.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 00h]
        3. 9.5.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 00h]
        4. 9.5.6.4  SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
        5. 9.5.6.5  Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
        6. 9.5.6.6  MODE_CNTRL Register (Address = 10h) [reset = 04h]
        7. 9.5.6.7  WD_CONFIG_1 Register (Address = 13h) [reset = 54h]
        8. 9.5.6.8  WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
        9. 9.5.6.9  WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
        10. 9.5.6.10 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0h]
        11. 9.5.6.11 WD_QA_ANSWER Register (Address = 2Eh) [reset = 0h]
        12. 9.5.6.12 WD_QA_QUESTION Register (Address = 2Fh) [reset = 0h]
        13. 9.5.6.13 STATUS (address = 40h) [reset = 00h]
        14. 9.5.6.14 INT_GLOBAL Register (Address = 50h) [reset = 0h]
        15. 9.5.6.15 INT_1 Register (Address = 51h) [reset = 0h]
        16. 9.5.6.16 INT_2 Register (Address = 52h) [reset = 40h]
        17. 9.5.6.17 INT_3 Register (Address 53h) [reset = 0h]
        18. 9.5.6.18 INT_CANBUS Register (Address = 54h) [reset = 0h]
        19. 9.5.6.19 INT_ENABLE_1 Register (Address = 56h) [reset = F3h]
        20. 9.5.6.20 INT_ENABLE_2 Register (Address = 57h) [reset = 3Fh]
        21. 9.5.6.21 INT_ENABLE_3 Register (Address =58h) [reset = 80h]
        22. 9.5.6.22 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
        23. 9.5.6.23 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
  10. 10Application Information Disclaimer
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Termination
    3. 10.3 Application Curves
  11. 11Power Supply Requirements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DMT|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Electrical Characteristics

Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, VSUP = 12 V, and RL = 60 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CAN Driver Electrical Characteristics
VO(D) Dominant output voltage
Bus biasing active		 CANH TXD = 0 V, 50 ≤ RL ≤ 65 Ω, CL = open, RCM = open
See Figure 8-2		 2.75 4.5 V
Dominant output voltage
Bus biasing active		 CANL 0.5 2.25 V
VO(R) Recessive output voltage
Bus biasing active		 TXD = VCCOUT, RL = open (no load), RCM = open
See Figure 8-2		 2 3 V
VSYM Driver symmetry
Bus biasing active
(VO(CANH) + VO(CANL) ) / VCCOUT		 RL = 60 Ω, CSPLIT = 4.7 nF, CL = Open, RCM = Open, TXD = 250 kHz, 1 Mhz, 2.5 MHz
See Figure 8-2		 0.9 1.1 V/V
VSYM_DC DC Driver symmetry
Bus biasing active
VCCOUT – VO(CANH) – VO(CANL)		 RL = 60 Ω, CL = open
See Figure 8-2		 –400 400 mV
VOD(DOM) Differential output voltage
Bus biasing active
Dominant		 CANH - CANL TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open
See Figure 8-2		 1.5 3 V
Differential output voltage
Bus biasing active
Dominant		 CANH - CANL TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open
See Figure 8-2		 1.4 3.3 V
Differential output voltage
Bus biasing active
Dominant		 CANH - CANL TXD = 0 V, RL = 2240 Ω, CL = open
See Figure 8-2		 1.5 5 V
VOD(REC) Differential output voltage
Bus biasing active
Bus biasing inactive
Recessive		 CANH - CANL TXD = VCCOUT, RL = open Ω, CL = open
See Figure 8-2		 –50 50 mV
VO(INACT) Pin output voltage
Bus biasing inactive		 CANH TXD = VCCOUT
RL = open (no load), CL = open
See Figure 8-2		 -0.1 0.1 V
CANL TXD = VCCOUT
RL = open (no load), CL = open
See Figure 8-2		 -0.1 0.1 V
VOD(STB) Differential output voltage
Bus biasing inactive		 CANH - CANL TXD = VCCOUT
RL = open (no load), CL = open
See Figure 8-2		 -0.2 0.2 V
IOS(DOM) Short-circuit steady-state output current
Bus biasing active
Dominant		 TXD = 0 V
-15 V ≤ V(CANH) ≤ 40 V
See Figure 8-2 and Figure 8-8		 –75 mA
Short-circuit steady-state output current
Bus biasing active
Dominant		 TXD = 0 V
-15 V ≤ V(CANL) ≤ 40 V
See Figure 8-2 and Figure 8-8		 75 mA
IOS(REC) Short-circuit steady-state output current
Bus biasing active
Recessive		 VBUS = CANH = CANL
-27 V ≤ VBUS ≤ 42 V
See Figure 8-2 and Figure 8-8		 –3 3 mA
CAN Receiver Electrical Characteristics
VIT(DOM) Receiver dominant state input voltage range
Bus biasing active		 -12 V ≤ VCM ≤ 12 V
See Figure 8-3 and Table 9-14		 0.9 8 V
VIT(REC) Receiver recessive state input voltage range
Bus biasing active		 -3 0.5 V
VHYS Hysteresis voltage for input threshold
Bus biasing active		 See Figure 8-3 and Table 9-14 80 140 mV
VDIFF(MAX) Maximum rating of VDIFF -5 10 V
VDIFF(DOM) Receiver dominant state input voltage range
Bus biasing inactive		 -12 V ≤ VCM ≤ 12 V
See Figure 8-3 and Table 9-14		 1.150 8 V
VDIFF(REC) Receiver recessive state input voltage range
Bus biasing inactive		 -3 0.4 V
VCM Common mode range See Figure 8-3 and Table 9-14 –12 12 V
IOFF(LKG) Power-off (unpowered) bus input leakage current VSUP = 0 V, CANH = CANL = 5 V 2.5 µA
CI Input capacitance to ground (CANH or CANL)(1) TXD = VCCOUT 20 pF
CID Differential input capacitance(1) TXD = VCCOUT 10 pF
RID Differential input resistance TXD = VCCOUT
-12 V ≤ VCM ≤ 12 V		 50 100 kΩ
RIN Input resistance (CANH or CANL) 25 50 kΩ
RIN(M) Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%		 V(CANH) = V(CANL) = 5 V –1 1 %
TXD Input Characteristics
VIH High level input voltage 0.7 VCCOUT
VIL Low level input voltage 0.3 VCCOUT
IIH High level input leakage current TXD = VCCOUT –1 0 1 µA
IIL Low level input leakage current TXD = 0 V –130 –15 µA
RPU Pull-up resistance 40 60 80 kΩ
ILKG(OFF) Unpowered leakage current TXD = 5.5 V, VSUP = 0 V –1 0 1 µA
CI Input Capacitance VIN = 0.4 x sin(2 × π × 2 × 106 × t) + 2.5 V 5 pF
RXD Output Characteristics
VOH High level output voltage IO = –2 mA. 0.8 VCCOUT
VOL Low level output voltage IO = 2 mA. 0.2 VCCOUT
RPU Pull-up resistance 40 60 80 kΩ
ILKG(OFF) Unpowered leakage curret RXD = 5.5 V, VSUP = 0 V -5 5 µA
INH Output Characteristics
ΔVH High level voltage drop INH with respect to VSUP IINH = –6 mA 0.5 1 V
ILKG(INH) Sleep mode leakage current INH = 0 V –0.5 0.5 µA
RPD Pull-down resistance Sleep Mode 2.5 4 6 MΩ
WAKE Input Characteristics
VIH High-level input voltage Sleep mode 4 V
VIL Low-level input voltage 2 V
IIL Low level input leakage current WAKE = 1 V 3 µA
VHYS Input hysteresis 800 1200 mV
nRST Bidirectional Characteristics
VIH High level input voltage 0.8 VCCOUT
VIL Low level input voltage 0.2 VCCOUT
VOL Low level output voltage IO = 2 mA. 0.2 VCCOUT
IIH High level input leakage current nRST = VCCOUT -1 1 µA
RPU Pull-up resistance to VCCOUT 160 240 320 kΩ
SDI Input Characteristics
VIH High level input voltage 0.8 VCCOUT
VIL Low level input voltage 0.2 VCCOUT
IIH High level input leakage current SDI = VCCOUT(2) -1 1 µA
IIL Low level input leakage current SDI = 0 V -130 -50 µA
RPU Pull-up resistance 40 60 80 kΩ
ILKG(OFF) Unpowered leakage current SDI = 5.5 V, VSUP = 0 V -1 1 µA
CIN Input capacitance 20 MHz 4 10 pF
SCLK Input Characteristics
VIH High level input voltage 0.7 VCCOUT
VIL Low level input voltage 0.3 VCCOUT
IIH High level input leakage current SCLK = VCCOUT(2) 50 130 µA
IIL Low level input leakage current SCLK = 0 V -1 1 µA
RPD Pull-down resistance 40 60 80 kΩ
ILKG(OFF) Unpowered leakage current SCLK = 5.5 V, VSUP = 0 V -1 1 µA
CIN Input capacitance 20 MHz 4 10 pF
nCS Input Characteristics
VIH High level input voltage High level input voltage High level input voltage 0.7 VCCOUT
VIL Low level input voltage Low level input voltage Low level input voltage 0.3 VCCOUT
IIH High level input leakage current nCS = VCCOUT -1 1 µA
IIL Low level input leakage current nCS = 0 V -130 -50 µA
RPU Pull-up resistor 40 60 80 kΩ
ILKG(OFF) Unpowered leakage current nCS = 5.5 V, VSUP = 0 V -1 1 µA
CIN Input capacitance 20 MHz 4 10 pF
SDO Output Characteristics
VOH High-level output voltage IOH = -2 mA 0.8 VCCOUT
VOL Low-level output voltage IOL = 2 mA 0.2 VCCOUT
ILKG(OFF) Unpowered leakage current VnCS = 5.5 V -1 1 µA
(1) Test according to ISO 11898-2:2003
(2) Note that there is an internal pull-up resistor to VCCOUT. If externally driven to a higher or lower voltage, the pin leakage measurement will be increased.