SLLSFF2B February 2022 – October 2024 TCAN1462-Q1
PRODUCTION DATA
The digital logic input and output levels for the TCAN1462-Q1 are CMOS levels with respect to VCC. For TCAN1462V-Q1, these are referred to VIO for compatibility with MCUs having 1.8 V, 2.5 V, 3.3 V, or 5 V supply.
Device Mode | TXD Input(1) | Bus Outputs | Driven Bus State(2) | |
---|---|---|---|---|
CANH | CANL | |||
Normal | Low | High | Low | Dominant |
High or open | High impedance | High impedance | Biased recessive | |
Standby | X | High impedance | High impedance | Biased to ground |
Device Mode | CAN Differential Inputs VID = VCANH – VCANL |
Bus State | RXD Pin |
---|---|---|---|
Normal | VID ≥ 0.9 V | Dominant | Low |
0.5 V < VID < 0.9 V | Undefined | Undefined | |
VID ≤ 0.5 V | Recessive | High | |
Standby | VID ≥ 1.15 V | Dominant | High Low if a remote wake event occurred See Figure 8-7 |
0.4 V < VID < 1.15 V | Undefined | ||
VID ≤ 0.4 V | Recessive | ||
Any | Open (VID ≈ 0 V) | Open | High |