SLLSFW8A June   2024  – December 2024 TCAN1472-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings, IEC Transients
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Characteristics
    6. 5.6  Supply Characteristics
    7. 5.7  Dissipation Ratings
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Signal Improvement
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Description
        1. 7.3.1.1 TXD
        2. 7.3.1.2 GND
        3. 7.3.1.3 VCC
        4. 7.3.1.4 RXD
        5. 7.3.1.5 VIO (TCAN1472V-Q1 only)
        6. 7.3.1.6 CANH and CANL
        7. 7.3.1.7 STB (Standby)
      2. 7.3.2 CAN Bus States
      3. 7.3.3 TXD Dominant Timeout (DTO)
      4. 7.3.4 CAN Bus Short-circuit Current Limiting
      5. 7.3.5 Thermal Shutdown (TSD)
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Unpowered Device
      8. 7.3.8 Floating pins
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Modes
      2. 7.4.2 Normal Mode
      3. 7.4.3 Standby Mode
        1. 7.4.3.1 Remote Wake Request via Wake-Up Pattern (WUP) in Standby Mode
      4. 7.4.4 Driver and Receiver Function
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 CAN Termination
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Bus Loading, Length and Number of Nodes
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Switching Characteristics

parameters valid over recommended operating conditions with -40℃ ≤ TJ ≤ 150℃ (Typical values are at VCC = 5 V, VIO = 3.3 V, Device ambient maintained at 27℃ ) unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Device Switching Characteristics
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant See Figure 6-4 , normal mode, VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)    90 145 ns
See Figure 6-4 , normal mode, VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)  95 155 ns
See Figure 6-4 , normal mode, VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)     110 170 ns
See Figure 6-4 , normal mode, VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)  125 190 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive See Figure 6-4 , normal mode, VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)  95 150 ns
See Figure 6-4 , normal mode, VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)  100 160 ns
See Figure 6-4 , normal mode, VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)  110 175 ns
See Figure 6-4 , normal mode, VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%)  125 190 ns
tMODE Mode change time, from normal to standby or from standby to normal See Figure 6-5
 		 30 µs
tWK_FILTER Filter time for a valid wake-up pattern See Figure 7-7  0.5 0.95 µs
tWK_TIMEOUT Bus wake-up timeout value See Figure 7-7    0.8 6 ms
Tstartup Time duration after VCC or VIO has cleared rising undervoltage threshold, and device can resume normal operation 1.5 ms
Tfilter(STB) Filter on STB pin to filter out any glitches 0.5 1 2 µs
Driver Switching Characteristics
tprop(TxD-busrec) Propagation delay time, low-to-high TXD edge to driver recessive (dominant to recessive) See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 4.5 V to 5.5 V 35 70 ns
See Figure 6-2  STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 3 V to 3.6 V 40 70 ns
See Figure 6-2  STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 2.25 V to 2.75 V 40 75 ns
See Figure 6-2  STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 1.71 V to 1.89 V 42 80 ns
tprop(TxD-busdom) Propagation delay time, high-to-low TXD edge to driver dominant (recessive to dominant) See Figure 6-2  , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 4.5 V to 5.5 V 35 75 ns
See Figure 6-2  STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 3 V to 3.6 V 35 75 ns
See Figure 6-2  STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 2.25 V to 2.75 V 40 80 ns
See Figure 6-2  STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 1.71 V to 1.89 V 42 80 ns
tsk(p) Pulse skew (|tprop(TxD-busrec) - tprop(TxD-busdom)|)  STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%),  See Figure 6-2  1 10 ns
tBUS_R Differential output signal rise time See Figure 6-2  , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%) 15 30 ns
tBUS_F Differential output signal fall time See Figure 6-2  , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%) 15 40 ns
tTXD_DTO Dominant timeout See Figure 6-6 , 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), STB = 0 V 1.2 4.0 ms
Receiver Switching Characteristics
tprop(busrec-RXD) Propagation delay time, bus recessive input to RXD high output (dominant to recessive) See Figure 6-3 , STB = 0 V,
45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 4.5 V to 5.5 V		 60 85 ns
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 3 V to 3.6 V 65 95 ns
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 2.25 V to 2.75 V 70 105 ns
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 1.71 V to 1.89 V 80 110 ns
tprop(busdom-RXD) Propagation delay time, bus dominant input to RXD low output (recessive to dominant) See Figure 6-3 , STB = 0 V,
45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 4.5 V to 5.5 V		 50 75 ns
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 3 V to 3.6 V 60 80 ns
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 2.25 V to 2.75 V 65 90 ns
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 1.71 V to 1.89 V 80 110 ns
tRXD_R RXD output signal rise time See Figure 6-3, STB = 0 V,
CL(RXD) = 15 pF(≤ ±1%)		 8 25 ns
tRXD_F RXD output signal fall time 7 30 ns
FD Timing Characteristics
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns See Figure 6-4, VCC = 4.5 V to 5.5 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 490 510 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns See Figure 6-4, VCC = 4.5 V to 5.5 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 190 210 ns
Bit time on CAN bus output pins with tBIT(TXD) = 125 ns See Figure 6-4, VCC = 4.5 V to 5.5 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 115 135 ns
tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns See Figure 6-4, VCC = 4.75 V to 5.25 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 470 520 ns
See Figure 6-4, VCC = 4.5 V to 5.5 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 470 525 ns
Bit time on RXD output pins with tBIT(TXD) = 200 ns See Figure 6-4, VCC = 4.75 V to 5.25 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 170 220 ns
See Figure 6-4, VCC = 4.5 V to 5.5 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 170 225 ns
Bit time on RXD output pins with tBIT(TXD) = 125 ns See Figure 6-4, VCC = 4.75 V to 5.25 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 95 145 ns
See Figure 6-4, VCC = 4.5 V to 5.5 V, STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω , CL = 100 pF, CL(RXD) = 15 pF
 		 95 150 ns
Signal Improvement Timing Characteristics
tPAS_REC_START Start time of passive recessive
phase		 Time duration from TXD rising 50% edge (<5ns slope) to start of passive recessive phase  420 530 ns
tACT_REC_START Start time of active signal improvement phase Time duration from TXD rising 50% edge (<5ns slope) to start of passive recessive phase 120 ns
tACT_REC_END End time of active signal improvement phase 355 ns
tΔBit(Bus) Transmitted bit width variation VCC = 4.75 V to 5.25 V, TXD <= 8Mbps, tΔBit(Bus) = tBit(Bus) - tBit(TxD)
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), See Figure 6-4		 –10 10 ns
VCC = 4.5 V to 5.5 V, TXD <= 8Mbps, tΔBit(Bus) = tBit(Bus) - tBit(TxD)
STB = 0 V, RL = 60 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), See Figure 6-4		 –10 10 ns
tΔBIT(RxD) Received bit width variation  VCC = 4.75 V to 5.25 V, TXD <= 8Mbps, tΔBIT(RxD) = tBit(RxD) - tBit(TxD)
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), CL(RXD) = 15 pF, See Figure 6-4		 –30 20 ns
VCC = 4.5 V to 5.5 V, TXD <= 8Mbps, tΔBIT(RxD) = tBit(RxD) - tBit(TxD)
STB = 0 V, RL = 60 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), CL(RXD) = 15 pF, See Figure 6-4		 –30 20 ns
tΔREC Receiver timing symmetry  VCC = 4.75 V to 5.25 V, TXD <= 8Mbps, tΔREC = tBit(RxD) - tBit(Bus)
STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), See Figure 6-4		 –20 15 ns
VCC = 4.5 V to 5.5 V, TXD <= 8Mbps, tΔREC = tBit(RxD) - tBit(Bus)
STB = 0 V, RL = 60 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), See Figure 6-4		 –20 15 ns