SLLSFW8 June 2024 TCAN1472-Q1
ADVANCE INFORMATION
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Device Switching Characteristics | ||||||
tPROP(LOOP1) | Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant | See Figure 6-4 , normal mode, VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) | 95 | 145 | ns | |
See Figure 6-4 , normal mode, VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) | 100 | 155 | ns | |||
See Figure 6-4 , normal mode, VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) | 105 | 170 | ns | |||
See Figure 6-4 , normal mode, VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) | 120 | 190 | ns | |||
tPROP(LOOP2) | Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive | See Figure 6-4 , normal mode, VIO = 4.5 V to 5.5 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) | 110 | 150 | ns | |
See Figure 6-4 , normal mode, VIO = 3 V to 3.6 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) | 115 | 160 | ns | |||
See Figure 6-4 , normal mode, VIO = 2.25 V to 2.75 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) | 120 | 175 | ns | |||
See Figure 6-4 , normal mode, VIO = 1.71 V to 1.89 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%) | 135 | 190 | ns | |||
tMODE | Mode change time, from normal to standby or from standby to normal | See Figure 6-5 |
30 | µs | ||
tWK_FILTER | Filter time for a valid wake-up pattern | See Figure 7-7 | 0.5 | 0.95 | µs | |
tWK_TIMEOUT | Bus wake-up timeout value | See Figure 7-7 | 0.8 | 6 | ms | |
Tstartup | Time duration after VCC or VIO hass cleared rising undervoltage threshold, and device can resume normal operation | 1.5 | ms | |||
Tfilter(STB) | Filter on STB pin to filter out any glitches | 0.5 | 1 | 2 | µs | |
Driver Switching Characteristics | ||||||
tprop(TxD-busrec) | Propagation delay time, low-to-high TXD edge to driver recessive (dominant to recessive) | See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 4.5 V to 5.5 V | 50 | 70 | ns | |
See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 3 V to 3.6 V | 50 | 70 | ns | |||
See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 2.25 V to 2.75 V | 55 | 75 | ns | |||
See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 1.71 V to 1.89 V | 55 | 80 | ns | |||
tprop(TxD-busdom) | Propagation delay time, high-to-low TXD edge to driver dominant (recessive to dominant) | See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 4.5 V to 5.5 V | 45 | 75 | ns | |
See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 3 V to 3.6 V | 50 | 75 | ns | |||
See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 2.25 V to 2.75 V | 50 | 80 | ns | |||
See Figure 6-2 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), VIO = 1.71 V to 1.89 V | 55 | 80 | ns | |||
tsk(p) | Pulse skew (|tprop(TxD-busrec) - tprop(TxD-busdom)|) | STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), See Figure 6-2 | 3.5 | 10 | ns | |
tBUS_R | Differential output signal rise time | See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%) | 20 | 30 | ns | |
tBUS_F | Differential output signal fall time | See Figure 6-2 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%) | 30 | 40 | ns | |
tTXD_DTO | Dominant timeout | See Figure 6-6 , 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), STB = 0 V | 1.2 | 4.0 | ms | |
Receiver Switching Characteristics | ||||||
tprop(busrec-RXD) | Propagation delay time, bus recessive input to RXD high output (dominant to recessive) | See Figure 6-3 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 4.5 V to 5.5 V |
60 | 85 | ns | |
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 3 V to 3.6 V | 65 | 95 | ns | |||
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 2.25 V to 2.75 V | 70 | 105 | ns | |||
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 1.71 V to 1.89 V | 80 | 110 | ns | |||
tprop(busdom-RXD) | Propagation delay time, bus dominant input to RXD low output (recessive to dominant) | See Figure 6-3 , STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 4.5 V to 5.5 V |
50 | 75 | ns | |
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 3 V to 3.6 V | 50 | 80 | ns | |||
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 2.25 V to 2.75 V | 55 | 90 | ns | |||
See Figure 6-3 STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), VIO = 1.71 V to 1.89 V | 65 | 110 | ns | |||
tRXD_R | RXD output signal rise time | See Figure 6-3, STB = 0 V, CL(RXD) = 15 pF(≤ ±1%) |
8 | 20 | ns | |
tRXD_F | RXD output signal fall time | 7 | 25 | ns | ||
Signal Improvement Timing Characteristics | ||||||
tPAS_REC_START | Start time of passive recessive phase |
Time duration from TXD rising 50% edge (<5ns slope) to start of passive recessive phase | 530 | ns | ||
tACT_REC_START | Start time of active signal improvement phase | Time duration from TXD rising 50% edge (<5ns slope) to start of passive recessive phase | 120 | ns | ||
tACT_REC_END | End time of active signal improvement phase | 355 | ns | |||
tΔBit(Bus) | Transmitted bit width variation | TXD <= 5Mbps square wave, tΔBit(Bus) = tBit(Bus) - tBit(TxD) STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), See Figure 6-4 |
–10 | 10 | ns | |
tΔBIT(RxD) | Received bit width variation | TXD <= 5Mbps square wave, tΔBIT(RxD) = tBit(RxD) - tBit(TxD) STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), CL(RXD) = 15 pF, See Figure 6-4 |
–30 | 20 | ns | |
tΔREC | Receiver timing symmetry | TXD <= 5Mbps square wave, tΔREC = tBit(RxD) - tBit(Bus) STB = 0 V, 45 Ω ≤ RL ≤ 65 Ω, CL = 100 pF (≤ ±1%), CL(RXD) = 15 pF (≤ ±1%), See Figure 6-4 |
–20 | 15 | ns |