SLLSFV7 July   2024 TCAN1473A-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings - IEC Specifications
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation Ratings
    7. 5.7  Power Supply Characteristics
    8. 5.8  Electrical Characteristics
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supply Pins
        1. 7.3.1.1 VSUP Pin
        2. 7.3.1.2 VCC Pin
        3. 7.3.1.3 VIO Pin
      2. 7.3.2 Digital Inputs and Outputs
        1. 7.3.2.1 TXD Pin
        2. 7.3.2.2 RXD Pin
        3. 7.3.2.3 nFAULT Pin
        4. 7.3.2.4 EN Pin
        5. 7.3.2.5 nSTB Pin
        6. 7.3.2.6 INH_MASK Pin
      3. 7.3.3 GND
      4. 7.3.4 INH Pin
      5. 7.3.5 WAKE Pin
      6. 7.3.6 CAN Bus Pins
      7. 7.3.7 Faults
        1. 7.3.7.1 Internal and External Fault Indicators
          1. 7.3.7.1.1 Power-Up (PWRON Flag)
          2. 7.3.7.1.2 Wake-Up Request (WAKERQ Flag)
          3. 7.3.7.1.3 Undervoltage Faults
            1. 7.3.7.1.3.1 Undervoltage on VSUP
            2. 7.3.7.1.3.2 Undervoltage on VCC
            3. 7.3.7.1.3.3 Undervoltage on VIO
          4. 7.3.7.1.4 CAN Bus Fault (CBF Flag)
          5. 7.3.7.1.5 TXD Clamped Low (TXDCLP Flag)
          6. 7.3.7.1.6 TXD Dominant State Timeout (TXDDTO Flag)
          7. 7.3.7.1.7 TXD Shorted to RXD Fault (TXDRXD Flag)
          8. 7.3.7.1.8 CAN Bus Dominant Fault (CANDOM Flag)
      8. 7.3.8 Local Faults
        1. 7.3.8.1 TXD Clamped Low (TXDCLP)
        2. 7.3.8.2 TXD Dominant Timeout (TXD DTO)
        3. 7.3.8.3 Thermal Shutdown (TSD)
        4. 7.3.8.4 Undervoltage Lockout (UVLO)
        5. 7.3.8.5 Unpowered Devices
        6. 7.3.8.6 Floating Terminals
        7. 7.3.8.7 CAN Bus Short-Circuit Current Limiting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating Mode Description
        1. 7.4.1.1 Normal Mode
        2. 7.4.1.2 Silent Mode
        3. 7.4.1.3 Standby Mode
        4. 7.4.1.4 Go-To-Sleep Mode
        5. 7.4.1.5 Sleep Mode
          1. 7.4.1.5.1 Remote Wake Request via Wake-Up Pattern (WUP)
          2. 7.4.1.5.2 Local Wake-Up (LWU) via WAKE Input Terminal
      2. 7.4.2 CAN Transceiver
        1. 7.4.2.1 CAN Transceiver Operation
          1. 7.4.2.1.1 CAN Transceiver Modes
            1. 7.4.2.1.1.1 CAN Off Mode
            2. 7.4.2.1.1.2 CAN Autonomous: Inactive and Active
            3. 7.4.2.1.1.3 CAN Active
          2. 7.4.2.1.2 Driver and Receiver Function Tables
          3. 7.4.2.1.3 CAN Bus States
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
      2. 8.1.2 Design Requirements
        1. 8.1.2.1 Bus Loading, Length and Number of Nodes
      3. 8.1.3 Detailed Design Procedure
        1. 8.1.3.1 CAN Termination
      4. 8.1.4 Application Curves
      5. 8.1.5 Power Supply Recommendations
      6. 8.1.6 Layout
        1. 8.1.6.1 Layout Guidelines
        2. 8.1.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DYY|14
  • DMT|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.6 Layout

Robust and reliable CAN node design may require special layout techniques depending on the application and automotive design requirements. Since transient disturbances have high frequency content and a wide bandwidth, high-frequency layout techniques should be applied during PCB design.